Logic encryption using on-chip memory cells

Patent metadata

Field	Value
Publication number	US-10438022-B2
Application number	US-201615381222-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Dec 16, 2016
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.

First claim

What is claimed is:

1. A protected circuit comprising:
a logic circuit providing one or more input nodes and one or more output nodes, the logic circuit comprising:
a network of logic elements; and
one or more logic encryption elements, and

a write circuit;

where each logic encryption element of the one or more logic encryption elements comprises a memory cell coupled with a configurable sub-circuit that is configured by a value stored in the memory cell, and
where a mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the memory cells of the one or more logic encryption elements match component values of a prescribed key vector,
where the write circuit is operable to write values to the memory cells of the one or more logic encryption elements.

2. The protected circuit of claim 1 , where each configurable sub-circuit of the one or more logic encryption elements comprises an XOR or XNOR logic gate having a value stored in the memory cell as a first input or a multiplexer having a value stored in the memory cell as a selection input.

3. The protected circuit of claim 1 , where each configurable sub-circuit of the one or more logic encryption elements comprises a path encryption element.

4. The protected circuit of claim 1 , where the one or more logic encryption elements are distributed in the network of logic elements.

5. The protected circuit of claim 1 , where each memory cell of the one or more logic encryption elements comprises a correlated electron switch (CES).

6. The protected circuit of claim 1 , where the memory cells of the one or more logic encryption elements store a first binary value upon fabrication, and where the write circuit is operable to write a second binary value to the memory cells of the one or more logic encryption elements but is unable to write the first binary value.

7. The protected circuit of claim 1 , further comprising an interface operable to receive a programming signal applied to the protected circuit, where the write circuit is responsive to the interface to write values to the memory cells of the one or more logic encryption elements dependent upon the programming signal.

8. A protected circuit comprising:
a logic circuit providing one or more input nodes and one or more output nodes, the logic circuit comprising:
a network of logic elements; and
one or more logic encryption elements,

where each logic encryption element of the one or more logic encryption elements comprises a memory cell coupled with a configurable sub-circuit that is configured by a value stored in the memory cell,
where a mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the memory cells of the one or more logic encryption elements match component values of a prescribed key vector, and
where each configurable sub-circuit of the one or more logic encryption elements comprises a multiplexer having a value stored in the memory cell as a selection input or an XOR or XNOR logic gate having a value stored in the memory cell as a first input.

9. A protected circuit comprising:
a plurality of logic elements;
a plurality of memory cells; and
a plurality of reconfigurable sub-circuits each configured by at least one value stored in a memory cell of the plurality of memory cells,

where the plurality of logic elements and the plurality of reconfigurable sub-circuits are coupled to form a logic circuit having one or more input nodes and one or more output nodes,
where a mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the plurality of memory cells match components of a prescribed key value, and
where one or more memory cells of the plurality of memory cells are programmable at leas one time.

10. The protected circuit of claim 9 , where a reconfigurable sub-circuit of the plurality of reconfigurable sub-circuits comprises a multiplexer having a value stored in a memory cell of the plurality of memory cells as a selection input.

11. The protected circuit of claim 9 , where a configurable sub-circuit of the plurality of reconfigurable sub-circuits comprises an XOR or XNOR logic gate having a value stored in a memory cell of the plurality of memory cells as a first input.

12. The protected circuit of claim 9 , where a configurable sub-circuit of the plurality of reconfigurable sub-circuits comprises a path encryption element.

13. The protected circuit of claim 9 , where the plurality of logic elements are distributed in the logic circuit.

14. The protected circuit of claim 9 , where at least one memory cell of the plurality of memory cells comprises a correlated electron switch (CES).

15. The protected circuit of claim 9 , where at least one memory cell of the plurality of memory cells comprises a non-volatile memory cell.

16. A method for copy protecting a logic circuit, the logic circuit comprising a plurality of logic elements, coupled via signal paths to form a logic network with one or more input nodes and one or more output nodes, and one or more logic encryption elements, where at least one signal path of the logic network includes a logic encryption element, of the one or more logic encryption elements, operable to encrypt a signal of the at least one signal path of the logic network or to encrypt one or more said signal paths of the logic network, where each logic encryption element of the one or more logic encryption elements comprises a memory cell coupled with a configurable sub-circuit that is configured by a value stored in the memory cell, the method comprising:
fabricating, by a first entity, an integrated circuit comprising the logic circuit and the one or more logic encryption elements; and
programming, by a second entity other than the first entity, the memory cells of the one or more logic encryption elements to match components of a prescribed key value,

where a mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the memory cells of the one or more logic encryption elements match components of the prescribed key value, and
where the logic circuit does not function correctly when values stored in the memory cells of the one or more logic encryption elements do not match components of the prescribed key value.

17. The method of claim 16 , where the memory cell of the one or more logic encryption elements comprise a correlated electron switch (CES) and where said programming the memory cells of the one or more logic encryption elements comprises:
applying a programming voltage across the CES; and
controlling an electrical current through the CES.

18. The method of claim 16 , where the integrated circuit further comprises a write circuit and a port that provides an interface to the write circuit, where said programming the memory cell of the one or more logic encryption elements comprises:
generating, external to the integrated circuit, a programming signal that encodes the prescribed key value; and
providing the programming signal to the port of the integrated circuit;

where the write circuit is responsive to the programming signal to program the memory cells of the one or more logic encryption elements with the prescribed key value.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Chandra Vikas
• Bhargava Mudit

Classifications

• G06F2221/2123

  Dummy operation · CPC title

• G09C1/06

  wherein elements corresponding to the signs making up the clear text are operatively connected with elements corresponding to the signs making up the ciphered text, the connections, during operation of the apparatus, being automatically and continuously permuted by a coding or key member · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• H04L9/06

  the encryption apparatus using shift registers or memories for block-wise {or stream} coding, e.g. DES systems {or RC4; Hash functions; Pseudorandom sequence generators} · CPC title