Low noise serial interfaces with gated clock

Patent metadata

Field	Value
Publication number	US-10437774-B2
Application number	US-201815876441-A
Country	US
Kind code	B2
Filing date	Jan 22, 2018
Priority date	Jan 26, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

First claim

What is claimed is:

1. A radio frequency system comprising:
a serial interface;
a radio frequency integrated circuit including a master device of the serial interface, the master device operable to send an interface command identifying a slave address; and
a first radio frequency component including a first slave device of the serial interface, the first slave device configured to receive an interface clock signal and an interface data signal from the serial interface, the first slave device including a register bank configured to store configuration data received from the interface data signal, a shift register configured to shift in the interface data signal, and a control circuit configured to control operation of the register bank, the control circuit operable to gate the interface clock signal to generate a first gated clock signal that controls the shift register and to further gate the first gated clock signal to generate a second gated clock signal that controls the register bank, the control circuit configured to prevent the first gated clock signal from toggling in response to determining that the slave address does not identify the first slave device.

2. The radio frequency system of claim 1 wherein the first radio frequency component further includes a radio frequency core circuit and an energy management core circuit configured to control the radio frequency core circuit based on the configuration data.

3. The radio frequency system of claim 2 wherein the serial interface provides a supply voltage and a ground voltage to the first radio frequency component, the control circuit operable to gate the interface clock signal to thereby prevent a harmonic of the interface clock signal from coupling to the radio frequency core circuit via the supply voltage and the ground voltage.

4. The radio frequency system of claim 1 wherein the first gated clock signal is further operable to control timing of the control circuit.

5. The radio frequency system of claim 4 wherein the control circuit includes a slave address detector configured to control gating of the interface clock signal based on comparing the slave address to a device user identification of the first slave device.

6. The radio frequency system of claim 5 wherein the control circuit further includes a start-up sequence detector configured to prevent the slave address detector from gating the interface clock signal in response to detecting a start-up sequence of the serial interface.

7. The radio frequency system of claim 1 wherein the control circuit is further configured to prevent the second gated clock signal from toggling until after the control circuit determines that the slave address identifies the first slave device.

8. The radio frequency system of claim 1 further comprising a second radio frequency component including a second slave device of the serial interface.

9. The radio frequency system of claim 1 wherein the control circuit is configured to cut off the interface clock signal from reaching the shift register in response to determining that the slave address does not identify the first slave device.

10. An integrated circuit for a radio frequency system, the integrated circuit comprising:
a radio frequency core circuit; and
an energy management core circuit configured to control the radio frequency core circuit based on configuration data received over a serial interface, the energy management core circuit including a slave device configured to receive an interface clock signal and an interface data signal from the serial interface, the slave device including a register bank configured to store the configuration data, a shift register configured to shift in the interface data signal, and a control circuit configured to control operation of the register bank, the control circuit operable to gate the interface clock signal to generate a first gated clock signal that controls the shift register and to further gate the first gated clock signal to generate a second gated clock signal that controls the register bank, the control circuit configured to prevent the first gated clock signal from toggling in response to determining that a slave address of an interface command received over the serial interface does not identify the slave device.

11. The integrated circuit of claim 10 wherein the first gated clock signal is further operable to control timing of the control circuit.

12. The integrated circuit of claim 11 wherein the control circuit includes a slave address detector configured to control gating of the interface clock signal based on comparing the slave address to a device user identification of the slave device.

13. The integrated circuit of claim 12 wherein the control circuit further includes a start-up sequence detector configured to prevent the slave address detector from gating the interface clock signal in response to detecting a start-up sequence of the serial interface.

14. The integrated circuit of claim 10 wherein the control circuit is further configured to prevent the second gated clock signal from toggling until after the control circuit determines that the slave address identifies the slave device.

15. A slave device of a serial interface, the slave device comprising:
a register bank configured to store configuration data received from an interface data signal of the serial interface;
a shift register configured to shift in the interface data signal; and
a control circuit configured to control operation of the register bank based on the interface data signal and an interface clock signal of the serial interface, the control circuit operable to gate the interface clock signal to generate a first gated clock signal that controls the shift register and to further gate the first gated clock signal to generate a second gated clock signal that controls the register bank, the control circuit configured to prevent the first gated clock signal from toggling in response to determining that a slave address of an interface command received over the serial interface does not identify the slave device.

16. The slave device of claim 15 wherein the control circuit is configured to cut off the interface clock signal from reaching the shift register in response to determining that the slave address does not identify the slave device.

17. The slave device of claim 15 wherein the first gated clock signal is further operable to control timing of the control circuit.

18. The slave device of claim 17 wherein the control circuit includes a slave address detector configured to control gating of the interface clock signal based on comparing the slave address to a device user identification of the slave device.

19. The slave device of claim 18 wherein the control circuit further includes a start-up sequence detector configured to prevent the slave address detector from gating the interface clock signal in response to detecting a start-up sequence of the serial interface.

20. The slave device of claim 15 wherein the control circuit is further configured to prevent the second gated clock signal from toggling until after the control circuit determines that the slave address identifies the slave device.

Assignees

• Skyworks Solutions Inc

Inventors

• Obkircher Thomas
• Blin Guillaume Alexandre
• Ross James Henry
• Roll Bryan J

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• H04B1/40

  Circuits · CPC title