Transition-minimized low speed data transfer

Patent metadata

Field	Value
Publication number	US-10437769-B2
Application number	US-201315032488-A
Country	US
Kind code	B2
Filing date	Dec 26, 2013
Priority date	Dec 26, 2013
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A method of transition minimized low speed data transfer is described herein. In an embodiment, a data rate of a set data to be transmitted on a data bus is determined. A one hot value is encoded on the data bus in response to a low data rate. An XOR operation is performed with a previous state of the data bus and the encoded one hot value. Additionally, a resulting value of the XOR operation is driven onto the data bus.

First claim

What is claimed is:

1. A system for transition minimized low speed data transfer, comprising:
a transmitter; and
a high speed data bus, wherein the high speed data bus is used for both transmission-minimized low-speed transfer and full-speed data transfer and wherein the transmitter encodes:
a first group of data from the high speed data bus into a one-hot value and XOR's the one hot value with a previous value on the high speed data bus;
a next group of data from the high speed data bus into a next one-hot value and XOR's the one hot value with a previous value on the high speed data bus; and
a final group of data from the high speed data bus into a final one-hot value and XOR's the one hot value with a previous value on the high speed data bus, wherein subsequent data for transmission is detected by a change on the high speed data bus without the use of a clock signal.

2. The system of claim 1 , wherein the one-hot value indicates a group of bits with a single high bit and all other bits are low.

3. The system of claim 1 , wherein the XOR operation is a non-return-to-zero line code.

4. The system of claim 1 , wherein the low data rate transmission avoids the need for the clock signal to toggle during low data rate transmission.

5. The system of claim 1 , wherein a data valid signal is used to differentiate between full and low-data rate modes.

6. The system of claim 1 , wherein the high speed data bus is of any width.

7. The system of claim 1 , wherein the transition minimized low speed data transfer is used with on-chip interfaces.

8. The system of claim 1 , wherein a subset of the full-speed data bus is used for transmission-minimized low-speed data transfer.

9. The system of claim 1 , wherein the use of a modified coding scheme for bus data transfer results in lower peak bus charging energies.

10. A method for transition minimized low speed data transfer, comprising:
determining a data rate of a set of data transmitted on a data bus;
encoding a one hot value of a first group of data from the data bus in response to a low data rate, wherein a data valid signal is used to differentiate between full and low-data rate modes of data transfer, and wherein the one-hot value and a previous value on the data bus are subject to an XOR operation and driving a resulting value of the XOR operation onto the data bus; and
encoding another one hot value of a second group of data from the data bus in response to a low data rate, wherein the another one-hot value and another previous value on the data bus are subject to another XOR operation and driving a second resulting value of the another XOR operation onto the data bus.

11. The method of claim 10 , wherein no clock signal is transmitted with the encoded one hot value.

12. The method of claim 10 , wherein the set of data is transmitted on a high speed data bus using less energy when compared to sending the same data as full rate data on the high speed data bus.

13. The method of claim 10 , wherein the low speed data transfer is automatically selected based on the data rate.

14. The method of claim 10 , wherein the transition minimized low speed data transfer is used with on-chip interfaces.

15. The method of claim 10 , wherein the data bus is a high speed data bus of any width.

16. The method of claim 10 , wherein the transition minimized low speed data transfer enables data to be transmitted using less energy when compared with a standard transmission scheme.

17. A method for transition minimized low speed data transfer, comprising:
capturing a previous state of a data bus;
performing an XOR operation with the previous state of the data bus and a current state of the data bus;
decoding a one hot value from the XOR operation into a first group of bits of data;
capturing a next previous state of the data bus;
performing a second XOR operation with the next previous state of the data bus and a next current state of the data bus; and
decoding a second one hot value from the second XOR operation into a second group of bits of data.

18. The method of claim 17 , wherein no clock signal is received on the data bus.

19. The method of claim 17 , wherein data is received on a high speed data bus and uses less energy when compared to full rate data on the high speed data bus.

20. The method of claim 17 , wherein the low speed data transfer is automatically based on a change in the bus state after a period of time passes from capturing the state of the data bus.

21. The method of claim 17 , wherein the transition minimized low speed data transfer is used with on-chip interfaces.

22. A tangible, machine-readable medium comprising code that, when executed, causes a processor to:
determine a data rate of a set of data transmitted on a data bus, wherein the data bus is used for both transmission-minimized low-speed transfer and full-speed data transfer;
encode a one hot value of a first group of data from the data bus in response to a low data rate, wherein the one-hot value and a previous value on the data bus are subject to an XOR operation and driving a resulting value of the XOR operation onto the data bus; and
encode another one hot value of a second group of data from the data bus in response to a low data rate, wherein the another one-hot value and another previous value on the data bus are subject to another XOR operation and driving a second resulting value of the another XOR operation onto the data bus.

23. The tangible, machine-readable medium of claim 22 , wherein no clock signal is transmitted with the encoded one hot value.

Assignees

• Intel Corp

Inventors

• Greenspan Daniel

Classifications

• G06F13/4243 Primary

  with synchronous protocol · CPC title

• G06F13/20

  for access to input/output bus · CPC title

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title

• G06F13/36

  for access to common bus or bus system · CPC title

• G06F13/42 Primary

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title