Partitioned interconnect slot for inter-processor operation

Patent metadata

Field	Value
Publication number	US-10437762-B2
Application number	US-201815872100-A
Country	US
Kind code	B2
Filing date	Jan 16, 2018
Priority date	Jan 16, 2018
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Systems and methods for providing a partitioned interconnect slot for inter-processor operation. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a processor comprising a first core and a second core; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to enable an Input/Output (I/O) device to communicate directly with the first core and the second core utilizing a single interconnect slot.

First claim

The invention claimed is:

1. An Information Handling System (IHS), comprising:
a processor comprising a first core and a second core;
a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to enable an Input/Output (I/O) device to communicate directly with the first core and the second core utilizing a single interconnect slot; and
a Basic Input/Output System (BIOS) coupled to the processor, the BIOS having program instructions stored thereon that, upon execution, cause the IHS to associate two or more interconnect slot entries with the single interconnect slot, wherein a first interconnect slot entry includes a first proximity domain construct that allows the first core to spawn a first interrupt or thread directed to a first portion of the single interconnect slot, and wherein a second interconnect slot entry includes a second proximity domain construct that allows the second core to spawn a second interrupt or thread directed to a second portion of the single interconnect slot.

2. The IHS of claim 1 , wherein the first and second cores access a single I/O device coupled to the single interconnect slot.

3. The IHS of claim 1 , wherein the program instructions, upon execution, further cause the IHS to enable the first core and the second core to communicate with the I/O device via the single interconnect slot in the absence of link traversal operations between the first core and the second core.

4. The IHS of claim 1 , wherein the first core and the second core share a non-volatile memory (NVM) bridge adapter.

5. The IHS of claim 4 , wherein the program instructions, upon execution, further cause the IHS to reduce latency of communication between (a) the first and second cores and (b) the NVM bridge adapter.

6. The IHS of claim 1 , further comprising a Basic Input/Output System (BIOS) coupled to the processor, the BIOS having program instructions stored thereon that, upon execution, cause the IHS to identify a type of the single interconnect slot.

7. A hardware memory device having program instructions stored thereon that, upon execution by an Information Handling System (IHS) having a processor comprising a first core and a second core, cause the IHS to:
associate two or more interconnect slot entries with an interconnect slot, wherein a first interconnect slot entry includes a first proximity domain construct that allows the first core to spawn a first interrupt or thread directed to a first portion of the interconnect slot, and wherein a second interconnect slot entry includes a second proximity domain construct that allows the second core to spawn a second interrupt or thread directed to a second portion of the interconnect slot;
enable the first core to communicate directly with an Input/Output (I/O) device via an interconnect slot; and
enable the second core to communicate directly with the I/O device via the interconnect slot.

8. The hardware memory device of claim 7 , wherein the direct communications exclude link traversal operations between the first core and the second core.

9. The hardware memory device of claim 7 , wherein the first core and the second core share a non-volatile memory (NVM) bridge adapter.

10. The hardware memory device of claim 9 , wherein the program instructions, upon execution, further cause the IHS to reduce latency of communication between (a) the first and second cores and (b) the NVM bridge adapter.

11. In an Information Handling System (IHS) having comprising a processor having at least a first core and a second core, a method comprising:
associating two or more interconnect slot entries with the interconnect slot, wherein a first interconnect slot entry includes a first proximity domain construct that allows the first core to spawn a first interrupt or thread directed to a first portion of the interconnect slot, and wherein a second interconnect slot entry includes a second proximity domain construct that allows the second core to spawn a second interrupt or thread directed to a second portion of the interconnect slot;
enabling the first core to communicate directly with an Input/Output (I/O) device via an interconnect slot; and
enabling the second core to communicate directly with the I/O device via the interconnect slot.

12. The method of claim 11 , wherein the direct communications exclude link traversal operations between the first core and the second core.

13. The method of claim 11 , wherein the first core and the second core share a non-volatile memory (NVM) bridge adapter.

14. The method of claim 13 , further comprising reducing latency of communication between (a) the first and second cores and (b) the NVM bridge adapter.

Assignees

• Dell Products Lp

Inventors

• Beckett John Christopher
• Hernandez Rich M
• Hormuth Robert Wayne
• Khatri Mukund P
• Varma Yogesh

Classifications

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F9/4403 Primary

  Processor initialisation · CPC title

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• G06F9/4406

  Loading of operating system · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title