Branchless instruction paging in reconfigurable fabric

Patent metadata

Field	Value
Publication number	US-10437728-B2
Application number	US-201816126107-A
Country	US
Kind code	B2
Filing date	Sep 10, 2018
Priority date	Feb 21, 2015
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Circular buffers containing instructions that enable the execution of operations on logical elements are described where data in the circular buffers is swapped to storage. The instructions comprise a branchless instruction set. Data stored in circular buffers is paged in and out to a second level memory. State information for each logical element is also saved and restored using paging memory. Instructions are provided to logical elements, such as processing elements, via circular buffers. The instructions enable a group of processing elements to perform operations implementing a desired functionality. That functionality is changed by updating the circular buffers with new instructions that are transferred from paging memory. The previous instructions can be saved off in paging memory before the new instructions are copied over to the circular buffers. This enables the hardware to be rapidly reconfigured amongst multiple functions.

First claim

What is claimed is:

1. A processor-implemented method for computation comprising:
paging data stored in a plurality of circular buffers, wherein the plurality of circular buffers controls one or more logical elements of a reconfigurable fabric, and where the paging comprises:
copying data from a first storage memory into the plurality of circular buffers where:
each of the plurality of circular buffers is coupled to at least one of the one or more logical elements;
the data provides instructions for the one or more logical elements;
as the circular buffers rotate, the instructions that are provided to the one or more logical elements change; and
the instructions comprise a branchless instruction set.

2. The method of claim 1 wherein instructions from a configuration ROM are used to operate the reconfigurable fabric while the paging is accomplished.

3. The method of claim 1 wherein the paging further comprises copying the data stored in the plurality of circular buffers into a second storage memory.

4. The method of claim 3 further comprising storing state information in the second storage memory.

5. The method of claim 3 wherein the copying, of the data stored in the plurality of circular buffers into a second storage memory, occurs before the copying of the data from a first storage memory into the plurality of circular buffers.

6. The method of claim 3 wherein the first storage memory comprises the second storage memory.

7. The method of claim 3 wherein the first storage memory and the second storage memory are substantially similar.

8. The method of claim 1 wherein the copying of the data from the first storage memory into the plurality of circular buffers causes data previously stored in the plurality of circular buffers to be overwritten.

9. The method of claim 1 wherein the data from the first storage memory includes state information.

10. The method of claim 1 wherein the data from the first storage memory includes instruction information.

11. The method of claim 1 wherein the instructions that change, that are delivered to the logical elements, provide a first sequence of operations by the logical elements.

12. The method of claim 11 wherein the data from the first storage memory provides a second set of instructions to the logical elements.

13. The method of claim 12 wherein the second set of instructions provides a second sequence of operations by the logical elements.

14. The method of claim 1 wherein the plurality of circular buffers comprises circular buffers of differing sizes.

15. The method of claim 14 wherein the circular buffers of differing sizes restart at a same time step.

16. The method of claim 1 wherein the branchless instruction set excludes if statements.

17. The method of claim 1 wherein the branchless instruction set precludes programming loops.

18. The method of claim 1 wherein the branchless instruction set excludes conditional jumps.

19. An apparatus for computation comprising:
a plurality of circular buffers where the plurality of circular buffers contains instructions for logical elements that are coupled to the plurality of circular buffers, and where the plurality of circular buffers contains a first copy of instructions comprising a branchless instruction set;
a storage memory containing a second copy of instructions for the plurality of circular buffers where the storage memory is coupled to the plurality of circular buffers; and
a set of switches and connections, coupled to the plurality of circular buffers, for transferring contents of the storage memory to the plurality of circular buffers.

20. The apparatus of claim 19 further comprising a further storage memory for a third copy of instructions for the plurality of circular buffers where the further storage memory is coupled to the plurality of circular buffers; and a further set of switches and connections for transferring contents of the further storage memory to the plurality of circular buffers.

21. The apparatus of claim 20 wherein the first copy of instructions is copied to a swapping memory before the third copy of instructions is moved into the plurality of circular buffers.

22. A computer program product embodied in a non-transitory computer readable medium for implementation of a logical calculation apparatus comprising:
code for designing a processing architecture including:
a plurality of circular buffers where the plurality of circular buffers contains instructions for logical elements that are coupled to the plurality of circular buffers, and where the plurality of circular buffers contains a first copy of instructions comprising a branchless instruction set;
a storage memory containing a second copy of instructions for the plurality of circular buffers where the storage memory is coupled to the plurality of circular buffers; and
a set of switches and connections, coupled to the plurality of circular buffers, for transferring contents of the storage memory to the plurality of circular buffers.

Assignees

• Wave Computing Inc

Inventors

• Nicol Christopher John

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F9/3816

  Instruction alignment, e.g. cache line crossing · CPC title

• G06N3/063

  using electronic means · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title