Memory mirroring

Patent metadata

Field	Value
Publication number	US-10437685-B2
Application number	US-201715783177-A
Country	US
Kind code	B2
Filing date	Oct 13, 2017
Priority date	Apr 25, 2014
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

First claim

What is claimed is:

1. A system comprising:
a memory controller; and
a memory channel coupled to the memory controller, the memory channel comprising:
a communication channel directly coupled to the memory controller;
a first dual-inline memory module (DIMM) directly coupled to the communication channel and having a first signal latency for signals sent from the memory controller to the first DIMM; and
a second DIMM directly coupled to the communication channel and having a second signal latency for signals sent from the memory controller to the second DIMM,
wherein the first signal latency is less than the second signal latency, and
wherein the memory controller is configured to enable storage of a primary copy of data within the first DIMM and a secondary copy of the data within the second DIMM in a single write operation by transmitting a copy of the data over the communication channel to the first DIMM and the second DIMM.

2. The system of claim 1 , wherein, in the single write operation, the memory controller is further configured to: transmit first write command and address signals to the first DIMM at a first time; and transmit second write command and address signals to the second DIMM at a second time, wherein the second time is delayed with respect to the first time based on the first and second signal latencies.

3. The system of claim 1 , wherein, in the single write operation, the memory controller is further configured to transmit same command and address signals concurrently to the first DIMM and the second DIMM.

4. The system of claim 1 , wherein the first DIMM and the second DIMM are coupled to different command and address buses.

5. The system of claim 1 , wherein, in the single write operation, the first DIMM is configured to start storing the data at a first time, and the second DIMM is configured to start storing the data at a second time, wherein the second time is delayed with respect to the first time based on the first and second signal latencies.

6. The system of claim 1 , wherein, in the single write operation, the memory controller is further configured to transmit a strobe signal concurrently to the first DIMM and the second DIMM.

7. The system of claim 3 , wherein, in the single write operation, the memory controller is further configured to activate chip selects of the first DIMM and the second DIMM respectively and sequentially based on a difference between the first and second signal latencies.

8. The system of claim 1 , wherein the communication channel directly coupled to the memory controller comprises:
a primary transmission line coupled to the memory controller;
a first secondary transmission line coupled to the primary transmission line and the first DIMM; and
a second secondary transmission line coupled to the primary transmission line and the second DIMM.

9. The system of claim 8 , wherein the communication channel directly coupled to the memory controller further comprises a splitter disposed on a circuit board, the splitter to split the primary transmission line into the first secondary transmission line and the second secondary transmission line.

10. A system comprising:
a memory controller; and
a memory channel comprising:
a communication channel directly coupled to the memory controller; and
a plurality of memory modules comprising a first module and a second module, wherein the first module and the second module are directly coupled to the communication channel, wherein the memory controller is configured to:
determine a first propagation delay for signals on the communication channel between the first module and the memory controller and a second propagation delay for signals on the communication channel between the second module and the memory controller, wherein the first propagation delay is less than the second propagation delay; and
send a data signal representing a data element in a single transmission to the first module and the second module via the communication channel, and
control the first module to store the data element according to the first propagation delay of the data signal on the communication channel and the second module to store the data element according to the second propagation delay of the data signal via the communication channel.

11. The system of claim 10 , wherein the first module and the second module are coupled to same command and address buses of the communication channel, and wherein further the memory controller is further configured to send a write command signal in a single transmission to the first module and the second module.

12. The system of claim 10 , wherein the memory controller is integrated in a central processing unit (CPU).

13. The system of claim 10 , wherein the communication channel directly coupled to the memory controller comprises:
a first set of wires coupled between to the memory controller and a splitter;
a second set of wires coupled between the splitter and the first module; and
a third set of wires coupled between the splitter and the second module, and
wherein data buses have different trace lengths between the memory controller and the first module and between the memory controller and the second module.

14. The system of claim 10 , wherein the first module comprises a dual in-line memory module (DIMM) and is assigned to store a primary copy of the data element, and wherein further the second module comprises a non-volatile memory module and is assigned to store a backup copy of the data element.

15. The system of claim 10 , wherein the first module and the second module are coupled to separate command and address buses of the communication channel, and wherein further the memory controller is further configured to send write command signals in respective transmissions to the first module and the second module, wherein the respective transmissions are timed based on a propagation delay.

16. A method comprising:
receiving at a memory controller a write request for storing a data element;
transmitting, by the memory controller over a communication channel directly coupled to a primary memory device and a backup memory device, a data signal representing the data element in a single write operation to store the data element at the primary memory device and the backup memory device, wherein the primary memory device has a first signal latency for the data signal from the memory controller and the backup memory device has a second signal latency for the data signal from the memory controller, wherein the first signal latency is less than the second signal latency; and
transmitting, by the memory controller, a control signal to enable storage of a copy of the data element by the primary memory device in view of the first signal latency and a copy of the data element by the backup memory device in view of the second signal latency.

17. The method of claim 16 , wherein the control signal is a chip select signal, and further comprising transmitting a write command signal by the memory controller to the primary memory device and the backup memory device in separate transmissions that are timed based on a propagation delay.

18. The method of claim 16 , further comprising transmitting by the memory controller a first clock signal to the primary memory device and a second clock signal to the backup memory device, wherein the first clock signal and the second clock signal are timed based on a propagation delay.

19. The method of claim 16 , further comprising transmitting by the memory controller an address signal to

Assignees

• Rambus Inc

Inventors

• Woo Steven
• Secker David A
• Kollipara Ravindranath

Classifications

• G06F11/20

  using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements · CPC title

• G06F13/4234

  being a memory bus · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F2201/84

  Using snapshots, i.e. a logical point-in-time copy of the data · CPC title

• G06F11/2058

  using more than 2 mirrored copies · CPC title