Dynamic core selection for heterogeneous multi-core systems

Patent metadata

Field	Value
Publication number	US-10437318-B2
Application number	US-201614986677-A
Country	US
Kind code	B2
Filing date	Jan 2, 2016
Priority date	Mar 11, 2011
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

First claim

The invention claimed is:

1. An apparatus for multi-core processing, the apparatus comprising:
a memory controller;
a first processor core of a first type to execute program code;
a second processor core of a second type different from the first type; and
a code distribution module to determine a performance metric of execution of the program code by the first processor core, determine a performance metric of the second processor core indicative of a predicted performance of the second processor core in executing the same program code, wherein to determine the performance metric of the second processor core comprises to apply the performance metric of the first processor core as an input to a prediction function, and switch execution of the program code from the first processor core to the second processor core in response to a determination that the performance metric of the second processor core is better than the performance metric of the first processor core or continue execution of the program code with the first processor core in response to a determination that the performance metric of the second processor core is not better than the performance metric of the first processor core.

2. The apparatus of claim 1 , further comprising an integrated circuit that includes the memory controller, the first processor core, the second processor core, and the code distribution module.

3. The apparatus of claim 1 , wherein the code distribution module is further to determine an amount of power consumed during execution of a code region.

4. The apparatus of claim 1 , wherein the code distribution module is further to power down the first processor core in response to a switch in execution of the program code from the first processor core to the second processor core.

5. The apparatus of claim 1 , wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core.

6. The apparatus of claim 1 , wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core.

7. The apparatus of claim 1 , wherein the memory controller is to manage a memory shared by the first processor core and the second processor core.

8. A method for processing by a multi-core processing system, the method comprising:
executing program code on a first processor core of the multi-core processing system;
determining a performance metric of execution of the program code by the first processor core;
determining a performance metric of a second processor core of the multi-core processing system indicative of a predicted performance of the second processor core in executing the same program code, wherein to determine the performance metric of the second processor core comprises to apply the performance metric of the first processor core as an input to a prediction function and wherein the first processor core is of a first type and the second processor core is of a second type different from the first type; and
switching execution of the program code from the first processor core to the second processor core in response to determining that the performance metric of the second processor core is better than the performance metric of the first processor core or continuing execution of the program code with the first processor core in response to a determination that the performance metric of the second processor core is not better than the performance metric of the first processor core.

9. The method of claim 8 , wherein the multi-core processing system is an integrated circuit that includes the first processor core, the second processor core, and a memory controller to manage a memory shared by the first processor core and the second processor core.

10. The method of claim 8 , further comprising determining an amount of power consumed during execution of a code region.

11. The method of claim 8 , further comprising powering down the first processor core in response to switching execution of the program code from the first processor core to the second processor core.

12. The method of claim 8 , wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core.

13. The method of claim 8 , wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core.

14. One or more non-transitory machine-readable storage media comprising a plurality of instructions embodied thereon that, in response to execution by one or more processors of a multi-core processing system, causes the one or more processors to:
execute program code on a first processor core of the multi-core processing system;
determine a performance metric of execution of the program code by the first processor core;
determine a performance metric of a second processor core of the multi-core processing system indicative of a predicted performance of the second processor core in executing the same program code, wherein to determine the performance metric of the second processor core comprises to apply the performance metric of the first processor core as an input to a prediction function and wherein the first processor core is of a first type and the second processor core is of a second type different from the first type; and
switch execution of the program code from the first processor core to the second processor core in response to a determination that the performance metric of the second processor core is better than the performance metric of the first processor core or continue execution of the program code with the first processor core in response to a determination that the performance metric of the second processor is not better than the performance metric of the first processor core.

15. The one or more non-transitory machine-readable storage media of claim 14 , wherein the multi-core processing system is an integrated circuit that includes the first processor core, the second processor core, and a memory controller to manage a memory shared by the first processor core and the second processor core.

16. The one or more non-transitory machine-readable storage media of claim 14 , wherein the plurality of instructions further causes the one or more processors to determine an amount of power consumed during execution of a code region.

17. The one or more non-transitory machine-readable storage media of claim 14 , wherein the plurality of instructions further causes the one or more processors to power down the first processor core in response to a switch in execution of the program code from the first processor core to the second processor core.

18. The one or more non-transitory machine-readable storage media of claim 14 , wherein the first processor core is an in-order processor core and the second processor core is an out-of-order processor core.

19. The one or more non-transitory machine-readable storage media of claim 14 , wherein the second processor core is an in-order processor core and the first processor core is an out-of-order processor core.

Assignees

• Intel Corp

Inventors

• Wu Youfeng
• Hu Shiliang
• Borin Edson
• Wang Cheng

Classifications

• G06F2201/865

  Monitoring of software · CPC title

• G06F2209/501

  Performance criteria · CPC title

• G06F2201/81

  Threshold · CPC title

• G06F2201/88

  Monitoring involving counting · CPC title

• G06F11/3452

  Performance evaluation by statistical analysis · CPC title