Channel switchover power multiplexer circuits, and methods of operating the same

Patent metadata

Field	Value
Publication number	US-10432184-B1
Application number	US-201816217658-A
Country	US
Kind code	B1
Filing date	Dec 12, 2018
Priority date	Aug 9, 2018
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Channel switchover power multiplexer circuits, and methods of operating the same are disclosed. An example power multiplexer a first transistor coupled to a first input, a second transistor coupled to the first transistor to couple a first voltage at the first input to an output, a third transistor coupled to a second input, a fourth transistor coupled to the third transistor to couple a second voltage at the second input to the output, a diode amplifier to provide a third voltage to a gate of the first transistor to block a reverse current, and a soft-start amplifier to provide a fourth voltage to a gate of the fourth transistor to turn on (with adjustable VOUT ramp rate) the fourth transistor with a constant ramp rate.

First claim

What is claimed is:

1. A power multiplexer, comprising:
a first transistor coupled to a first input;
a second transistor coupled to the first transistor to selectively couple a first voltage at the first input to an output;
a third transistor coupled to a second input;
a fourth transistor coupled to the third transistor to selectively couple a second voltage at the second input to the output;
a diode amplifier to provide a third voltage to a gate of the first transistor to block a reverse current; and
a soft-start amplifier to provide a fourth voltage to a gate of the fourth transistor to turn on the fourth transistor with a constant ramp rate.

2. The power multiplexer of claim 1 , further including:
a comparator to, while the diode amplifier provides the third voltage to the gate of the first transistor, detect a drop in a fifth voltage at the output; and
a one-shot generator to, while the diode amplifier provides the third voltage to the gate of the first transistor, form a pulse to temporarily turn on the first transistor.

3. The power multiplexer of claim 1 , wherein the first transistor is connected to the second transistor to pass current bidirectionally between the first input and the output.

4. The power multiplexer of claim 1 , further including:
a second soft-start amplifier to provide a fifth voltage to a gate of the second transistor to turn on the second transistor with a constant ramp rate; and
a capacitor coupled to a ground, and coupled to an input of the soft-start amplifier and an input of the second soft-start amplifier.

5. The power multiplexer of claim 1 , further including a controller to switch the power multiplexer from (a) a first state wherein the first voltage at the first input coupled to the output to (b) a second state wherein the second voltage at the second input coupled to the output by:
enabling the diode amplifier, and
enabling the soft-start amplifier.

6. The power multiplexer of claim 5 , where the controller is to:
disable the diode amplifier; and
disable the soft-start amplifier.

7. The power multiplexer of claim 6 , further including:
a second diode amplifier to provide a fifth voltage to a gate of the third transistor to block a reverse current; and
a second soft-start amplifier to provide a sixth voltage to a gate of the second transistor to turn on the second transistor with a constant ramp rate,
wherein the controller is to switch the power multiplexer from the first state to the second state by:
enabling the second diode amplifier, and
enabling the second soft-start amplifier.

8. The power multiplexer of claim 1 , further including:
a first driver coupled to a gate of the first transistor;
a second driver coupled to a gate of the second transistor;
a first pull-down coupled to the gate of the second transistor;
a third driver coupled to a gate of the third transistor;
a fourth driver coupled to the gate of the fourth transistor;
a second pull-down coupled to the gate of the fourth transistor; and
a controller to:
in a first state, enable the first driver, enable the second driver, disable the third driver, disable the fourth driver, disable the soft-start amplifier, disable the diode amplifier, disable the first pull-down, and enable the second pull-down to couple the first voltage at the first input to the output;
in a second state, disable the first driver, disable the second driver, enable the third driver, enable the fourth driver, disable the soft-start amplifier, disable the diode amplifier, enable the first pull-down, and disable the second pull-down to couple the second voltage at the second input to the output; and
transition the power multiplexer from the first state to the second state by disabling the first pull-down, disabling the second pull-down, enabling the diode amplifier, enabling the soft-start amplifier, disabling the first driver, enabling the second driver, enabling the third driver, and disabling the fourth driver.

9. A method of controlling a power multiplexer circuit, the method comprising:
enabling a soft-start amplifier to turn on a first transistor, the first transistor having a drain connected to a drain of a second transistor to form a first channel between a first input and an output;
enabling a diode amplifier to regulate a gate voltage of a third transistor, the third transistor having a drain connected to a drain of a fourth transistor to form a second channel between a second input and an output; and
when the first transistor has turned on:
disabling the soft-start amplifier,
enabling a first driver to hold the first transistor on, and
disabling the diode amplifier.

10. The method of controlling the power multiplexer circuit of claim 9 , further including enabling a second driver to hold the second transistor on when the soft-start amplifier is enabled.

11. The method of controlling the power multiplexer circuit of claim 9 , when an output voltage at the output satisfies a threshold, disabling the diode amplifier, and enabling a boost driver to form a pulsed gate voltage for the third transistor.

12. The method of controlling the power multiplexer circuit of claim 9 , further including when the first transistor has turned on, enabling a pull-down to disable the third transistor and the fourth transistor.

13. The method of controlling the power multiplexer circuit of claim 9 , wherein the diode amplifier regulates the gate voltage of the third transistor based on a comparison of an output voltage at the output and an input voltage.

14. The method of controlling the power multiplexer circuit of claim 9 , further including charging and discharging a capacitor to generate an input for the soft-start amplifier.

15. A power multiplexer circuit, comprising:
a first transistor having a source coupled to a first power multiplexer input;
a second transistor having a drain coupled to a drain of the first transistor, and a source coupled to a power multiplexer output;
a third transistor having a source coupled to a second power supply input;
a fourth transistor having a drain coupled to a drain of the third transistor, and a source coupled to the power multiplexer input;
a first amplifier having an output coupled to a gate of the first transistor, a first input coupled to the first power multiplexer input via a first voltage source, and a second input coupled to the power multiplexer output;
a second amplifier having an output coupled to a gate of the fourth transistor;
a capacitor having a first terminal coupled to an input of the second amplifier and to a charging source; and
a controller coupled to an enable input of the first amplifier and to an enable input of the second amplifier.

16. The power multiplexer circuit of claim 15 , wherein the first transistor is a first metal-oxide semiconductor field-effect transistor (MOSFET), the second transistor is a second MOSFET, the third transistor is a third MOSFET, and the fourth transistor is a fourth MOSFET.

17. The power multiplexer circuit of claim 16 , further including:
a comparator having a first input coupled to the power multiplexer output, a second input coupled to the first power multiplexer input via a second voltage source, and an output; and
a logic gate having a first input coupled to the output of the comparator, an enable input coupled to the controller, and an output coupled to an enable input of the first amplifier.

18. The power multiplexer circuit of claim 17 , further including:
a pulse generator having an input coupled to the output of the compara

Assignees

• Texas Instruments Inc

Inventors

• Choi Jae Won
• Beck Sungho
• Turkson Richard
• Klarenbeek Johnny
• Li Bixia

Classifications

• H03K2217/0009

  AC switches, i.e. delivering AC power to a load · CPC title

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03K17/163

  Soft switching · CPC title

• H03K5/24 Primary

  the characteristic being amplitude · CPC title

• H03K17/002 Primary

  Switching arrangements with several input- or output terminals (code converters H03M5/00, H03M7/00) · CPC title