Low overhead copy engine fault and switch mechanism

Patent metadata

Field	Value
Publication number	US-10430356-B2
Application number	US-201715582459-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Apr 28, 2017
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.

First claim

What is claimed is:

1. A parallel processor, comprising:
a memory management unit; and
a copy engine coupled to the memory management unit, wherein the copy engine:
receives a first copy operation included in a plurality of copy operations that includes a first set of copy commands;
executes, by the copy engine, a first copy command included in the first set of copy commands;
receives an acknowledgement from the memory management unit indicating that the first copy command caused a page fault;
stores the first set of copy commands to the memory including the first copy command that caused the page fault;
after the page fault has been resolved, loads the first set of copy commands from the memory; and
re-executes, by the copy engine, the first copy command.

2. The parallel processor of claim 1 , wherein the copy engine further receives, from a host interface, a plurality of copy operations that includes the first copy operation, wherein an original copy operation has been split by the host interface into the plurality of copy operations.

3. The parallel processor of claim 1 , wherein an original copy operation associated with a first memory range has been split into the plurality of copy operations, and each copy operation included in the plurality of copy operations is associated with a different memory range that is smaller than the first memory range.

4. The parallel processor of claim 1 , wherein the copy engine further:
receives, from a host interface, a context load request associated with the first copy operation;
wherein the first set of copy commands is loaded and the first copy command is re-executed in response to receiving the context load request.

5. The parallel processor of claim 4 , wherein the first copy operation is associated with a first channel, and wherein the copy engine further:
receives a second copy operation included in the plurality of copy operations that includes a second set of copy commands, wherein the second copy operation is associated with a second channel; and
executes, by the copy engine, a second copy command included in the second set of copy commands.

6. The parallel processor of claim 4 , wherein the host interface:
determines that the page fault has been resolved; and
in response, transmits the context load request to the copy engine.

7. The parallel processor of claim 4 , wherein the context load request includes a channel identifier that identifies a channel that caused the page fault.

8. The parallel processor of claim 4 , wherein the context load request includes a pointer to a memory location where the first set of copy commands is stored.

9. A computer-implemented method for resolving page faults generated by a copy engine, the method comprising:
receiving a first copy operation included in a plurality of copy operations that includes a first set of copy commands;
executing, by the copy engine, a first copy command included in the first set of copy commands that results in a page fault;
storing the first set of copy commands to the memory including the first copy command that results in the page fault;
after the page fault has been resolved, loading the first set of copy commands from the memory; and
re-executing, by the copy engine, the first copy command.

10. The computer-implemented method of claim 9 , further comprising:
making a determination that a second copy operation received prior to the first copy operation is committed to complete; and
in response to the determination, reporting the page fault to a host interface.

11. The computer-implemented method of claim 9 , further comprising:
receiving, from a host interface, a context load request associated with the first copy operation;
wherein the first set of copy commands is loaded and the first copy command is re-executed in response to receiving the context load request.

12. The computer-implemented method of claim 11 , wherein the first copy operation is associated with a first channel, and further comprising:
receiving a second copy operation included in the plurality of copy operations that includes a second set of copy commands, wherein the second copy operation is associated with a second channel; and
executing, by the copy engine, a second copy command included in the second set of copy commands.

13. The computer-implemented method of claim 11 , wherein the host interface:
determines that the page fault has been resolved; and
in response, transmits the context load request to the copy engine.

14. The computer-implemented method of claim 11 , wherein the context load request includes a channel identifier that identifies a channel that caused the page fault.

15. The computer-implemented method of claim 11 , wherein the context load request includes a pointer to a memory location where the first set of copy commands is stored.

16. The computer-implemented method of claim 9 , wherein the copy engine further receives, from a host interface, a plurality of copy operations that includes the first copy operation, wherein an original copy operation has been split by the host interface into the plurality of copy operations.

17. A computer-implemented method for resolving page faults generated by a copy engine, the method comprising:
receiving a first copy operation included in a plurality of copy operations that includes a first set of copy commands;
executing, by the copy engine, a first copy command included in the first set of copy commands;
receiving an acknowledgement from a memory management unit indicating that the first copy command caused a page fault;
storing the first set of copy commands to the memory including the first copy command that caused the page fault;
after the page fault has been resolved, loading the first set of copy commands from the memory; and
re-executing, by the copy engine, the first copy command.

18. The computer-implemented method of claim 17 , further comprising receiving, from a host interface, a plurality of copy operations that includes the first copy operation, wherein an original copy operation has been split by the host interface into the plurality of copy operations.

19. The computer-implemented method of claim 17 , wherein an original copy operation associated with a first memory range has been split into the plurality of copy operations, and each copy operation included in the plurality of copy operations is associated with a different memory range that is smaller than the first memory range.

20. The computer-implemented method of claim 17 , further comprising:
making a determination that a second copy operation that includes a second set of copy commands follows the first copy operation; and
in response to the determination, storing the second set of copy commands to the memory.

Assignees

• Nvidia Corp

Inventors

• Rashid M Wasiur
• Evans Jonathon
• Ward Gary
• Johnson Philip Browning

Classifications

• G06F2212/1041

  Resource optimization · CPC title

• G06F12/109 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title