Non-volatile cache and non-volatile storage medium using single bit and multi bit flash memory cells or different programming parameters

Patent metadata

Field	Value
Publication number	US-10430328-B2
Application number	US-201414487905-A
Country	US
Kind code	B2
Filing date	Sep 16, 2014
Priority date	Sep 16, 2014
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Systems and methods for configuring, controlling and operating a non-volatile cache are disclosed. A host system may poll a memory system as to the memory system's configuration of its non-volatile cache. Further, the host system may configure the non-volatile cache on the memory system, such as the size of the non-volatile cache and the type of programming for the non-volatile cache (e.g., whether the non-volatile cache is programmed according to SLC or the type of TRIM used to program cells in the non-volatile cache). Moreover, responsive to a command from the host to size the non-volatile cache, the memory system may over or under provision the cache. Further, the host may control operation of the non-volatile cache, such as by sending selective flush commands.

First claim

What is claimed is:

1. A storage device comprising:
a memory comprising a non-volatile cache and a non-volatile storage medium; and
a controller in communication with the memory, the controller configured to:
receive, from a host system, a host system cache command, the host system cache command comprising a command to the storage device containing one or more cache criteria for configuring or controlling the non-volatile cache, the one or more cache criteria being generated by the host system and responsive to analysis by the host system of the memory in the storage device;
receive host data in host data commands;
control operation of the non-volatile cache with respect to handling host data received in the host data commands according to the one or more cache criteria contained in the host system cache command;
control operation of the non-volatile storage medium according to storage medium criteria,
wherein the one or more cache criteria is different from the storage medium criteria;
program cells in the non-volatile cache according to a first TRIM set; and
program cells in the non-volatile storage medium according to a second TRIM set,
wherein the first TRIM set includes at least one TRIM parameter and the second TRIM set includes at least one other TRIM parameter different from the at least one TRIM parameter of the first TRIM set, and wherein the cells in the non-volatile cache are programmed according to the at least one TRIM parameter of the first TRIM set and the cells in the non-volatile storage medium are programmed according to the at least one other TRIM parameter of the second TRIM set.

2. The storage device of claim 1 , wherein the controller is configured to program cells in the non-volatile cache to a first number of bits per cell;
wherein the controller is further configured to program cells in the storage medium to a second number of bits per cell; and
wherein the first number of bits per cell is different from the second number of bits per cell.

3. The storage device of claim 2 , wherein the controller is configured to program the cells in the non-volatile cache for single-level cells; and
wherein the controller is configured to program the cells in the non-volatile storage medium for multi-level cells.

4. The storage device of claim 1 , wherein the at least one TRIM parameter of the first TRIM set includes at least one of a program voltage, a set-up voltage, and a program pulse width.

5. The storage device of claim 1 , wherein the controller is configured to use the host system cache command to configure the non-volatile cache.

6. The storage device of claim 5 , wherein the controller is configured to program a respective memory cell in the non-volatile storage medium to store multiple bits;
wherein the host system cache command comprises an indication that at least a part of the non-volatile cache is single-level cell; and
wherein, in response to receipt of the host system cache command, the cache operation circuitry is configured to program a respective memory cell in the non-volatile cache to store a single bit.

7. The storage device of claim 4 , wherein the memory comprises a plurality of dies, each of the dies comprising a plurality of blocks;
wherein the non-volatile cache is allocated to a first portion of a block in each of the plurality of dies, the first portion being less than an entire respective block;
wherein a second portion of block comprising a remainder of the block is allocated to the non-volatile storage medium;
wherein programming of the first portion of the block is according to the first TRIM set; and
wherein programming of the second portion of the block is according to the second TRIM set.

8. A method comprising:
receiving, at a storage device having a controller in communication with a memory comprising a non-volatile cache and a non-volatile storage medium, a host system cache command from a host system to configure a non-volatile cache, the host system cache command comprising a command to a storage device containing one or more cache criteria for configuring or controlling the non-volatile cache, the one or more cache criteria being generated by the host system and responsive to analysis by the host system of the memory in the storage device;
updating, by the storage device, non-volatile cache criteria with the one or more cache criteria;
controlling the non-volatile cache according to the non-volatile cache criteria;
controlling the non-volatile storage medium according to storage medium criteria,
wherein the non-volatile cache criteria is different from the storage medium criteria;
programming cells in the non-volatile cache according to a first TRIM set; and
programming cells in the non-volatile storage medium according to a second TRIM set,
wherein the first TRIM set includes at least one TRIM parameter and the second TRIM set includes at least one other TRIM parameter different from the at least one TRIM parameter of the first TRIM set, and wherein the cells in the non-volatile cache are programmed according to the at least one TRIM parameter of the first TRIM set and the cells in the non-volatile storage medium are programmed according to the at least one other TRIM parameter of the second TRIM set.

9. The method of claim 8 , wherein the one or more cache criteria comprises a first number of bits per cell;
wherein programming cells in the non-volatile cache is according to the first number of bits per cell;
wherein programming cells in the storage medium is according to a second number of bits per cell; and
wherein the first number of bits per cell is different from the second number of bits per cell.

10. The method of claim 9 , wherein programming the cells in the non-volatile cache is for single-level cells; and
wherein programming the cells in the storage medium for multi-level cells.

11. The method of claim 8 , wherein the at least one TRIM parameter of the first TRIM set includes at least one of a program voltage, a set-up voltage, and a program pulse width.

12. The method of claim 8 , wherein programming a respective memory cell in the non-volatile storage medium stores multiple bits;
wherein the one or more cache criteria in the host system cache command comprises an indication that at least a part of the non-volatile cache is single-level cell; and
wherein, in response to receipt of the host system cache command:
the non-volatile storage cache criteria is updated with the indication that at least a part of the non-volatile cache is single-level cell; and
the programming of a respective memory cell in the non-volatile cache is to store a single bit.

13. The method of claim 8 , wherein the non-volatile cache is allocated to an entire one or more blocks in the memory.

14. The method of claim 8 , wherein the memory comprises a plurality of dies, each of the dies comprising a plurality of blocks;
wherein the non-volatile cache is allocated to a first portion of a block in each of the plurality of dies, the first portion being less than an entire respective block; and
wherein a second portion of block comprising a remainder of the block is allocated to the non-volatile storage medium.

15. The storage device of claim 1 , wherein the one or more cache criteria in the host system control command comprises fullness criteria; and
wherein the controller is configured to use the fullness criteria to determine a fullness of the non-volatile cache.

16. The storage device of claim 1 , wherein the host system cache command comprises a host system control command configured to control operation

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Sela Rotem
• Sapir Miki
• Shaharabany Amir
• Oshinsky Hadas
• Abraham Rafi
• Baram Elad

Classifications

• G06F2212/214

  Solid state disk · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F2212/1016

  Performance improvement · CPC title