Monitoring correctable errors on a bus interface to determine whether to redirect input/output (I/O) traffic from a first processing unit to a second processing unit

Patent metadata

Field	Value
Publication number	US-10430264-B2
Application number	US-201715612791-A
Country	US
Kind code	B2
Filing date	Jun 2, 2017
Priority date	Jun 2, 2017
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Provided are a computer program product for managing bus interface errors in a storage system coupled to a host and storage. A determination is made as to whether a first number of correctable errors on a first bus interface, connecting a first processing unit to the storage, exceeds a second number of correctable errors on a second bus interface, connecting a second processing unit to the storage, by a difference threshold. The correctable errors in the first and second bus interfaces are detected and corrected in the first and second bus interfaces by first hardware and second hardware, respectively. In response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, at least a portion of Input/Output (I/O) requests are redirected to a second processing unit using the second bus interface to connect to the storage.

First claim

What is claimed is:

1. A computer program product for managing bus interface errors in a storage system coupled to a host and storage, the computer program product comprising a computer readable storage medium having computer readable program code embodied therein that is executable to perform operations, the operations comprising:
determining whether a first number of correctable errors on a first bus interface, connecting a first processing unit to the storage, exceeds a second number of correctable errors on a second bus interface, connecting a second processing unit to the storage, by a difference threshold, wherein the correctable errors in the first and second bus interfaces are detected and corrected in the first and second bus interfaces by first hardware of the first bus interface and second hardware of the second bus interface, respectively; and
in response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, redirecting at least a portion of Input/Output (I/O) requests to the second processing unit using the second bus interface to connect to the storage.

2. The computer program product of claim 1 , wherein in response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, the operations further comprise:
processing a first portion of the I/O requests from the host at the first processing unit, wherein the redirecting the at least the portion of I/O requests redirects a second portion of the I/O requests from the host to the second processing unit.

3. The computer program product of claim 1 , wherein a host adaptor receives the I/O requests from a connected host, sends the I/O requests to the first processing unit, and performs the operations of determining whether the first number of correctable errors exceeds the second number of correctable errors and the redirecting the at least the portion of the I/O requests, wherein the host adaptor redirects the at least the portion of the I/O requests to the second processing unit over the first bus interface.

4. The computer program product of claim 3 , wherein in response to the host adaptor determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, further performing:
sending a first portion of the I/O requests from the host to the first processing unit, wherein the redirecting the at least the portion of I/O requests redirects a second portion of the I/O requests to the second processing unit.

5. The computer program product of claim 4 , wherein the host adaptor is in a first I/O bay, which includes a first device adaptor, to which the first bus interface connects and wherein a second device adaptor is in a second I/O bay to which the second bus interface connects, wherein a default assignment assigns the first processing unit to use the first device adaptor and assigns the second processing unit to use the second device adaptor.

6. The computer program product of claim 3 , wherein the determining whether the first number of correctable errors exceeds the second number of correctible errors by the difference threshold and the redirecting the at least the portion of I/O requests is performed by the first processing unit, wherein the redirecting the at least the portion of the I/O requests comprises the first processing unit transferring the at least the portion of the I/O requests to the second processing unit to process.

7. The computer program product of claim 3 , wherein in response to the first processing unit determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, further performing:
processing a first portion of the I/O requests from the host at the first processing unit, wherein the redirecting the at least the portion of I/O requests redirects a second portion of the I/O requests to the second processing unit.

8. The computer program product of claim 1 , wherein the correctable errors are logged in the first and the second bus interfaces, wherein the first number and the second number of correctable errors on the first and the second bus interfaces are determined from registers in the first and the second bus interfaces, respectively, logging the correctable errors.

9. A system for managing bus interface errors in a storage system coupled to a host and a storage, comprising:
a first processing unit;
a second processing unit;
a first bus interface connecting the first and second processing units to the storage and including first hardware to detect and correct correctable errors;
a second bus interface connecting the first and second processing units to the storage and including second hardware to detect and correct correctable errors;
a computer readable storage medium having computer readable program code executed by at least the first processing unit and the second processing unit to perform operations, the operations comprising:
determining whether a first number of correctable errors on the first bus interface exceeds a second number of correctable errors on the second bus interface; and
in response to determining that the first number of correctable errors exceeds the second number of correctable errors by a difference threshold, redirecting at least a portion of Input/Output (I/O) requests to the second processing unit using the second bus interface to connect to the storage.

10. The system of claim 9 , wherein in response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, the operations further comprise:
processing a first portion of the I/O requests from the host at the first processing unit, wherein the redirecting the at least the portion of I/O requests redirects a second portion of the I/O requests from the host to the second processing unit.

11. The system of claim 9 , further including:
a host adaptor to receive the I/O requests from a connected host, to send the I/O requests to the first processing unit, and to perform the determining whether the first number of correctable errors exceeds the second number of correctable errors and the redirecting the at least the portion of the I/O requests, wherein the host adaptor redirects the at least the portion of the I/O requests to the second processing unit over the first bus interface.

12. The system of claim 11 , wherein in response to the host adaptor determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, the host adaptor further performs:
sending a first portion of the I/O requests from the host to the first processing unit, wherein the redirecting the at least the portion of I/O requests redirects a second portion of the I/O requests to the second processing unit.

13. The system of claim 12 , further comprising:
a first I/O bay including the host adaptor;
a first device adaptor in the first I/O bay to which the first bus interface connects;
a second I/O bay; and
a second device adaptor in the second I/O bay to which the second bus interface connects, wherein a default assignment assigns the first processing unit to use the first device adaptor and assigns the second processing unit to use the second device adaptor.

14. The system of claim 11 , wherein the determining whether the first number of correctable errors exceeds the second number of correctible errors by the difference threshold and the redirecting the at least the p

Assignees

• IBM

Inventors

• Borlick Matthew G
• Gupta Lokesh M
• Nguyen Trung N

Classifications

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G06F11/076 Primary

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F2201/81

  Threshold · CPC title

• G06F11/0727 Primary

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/0754

  by exceeding limits · CPC title