Voltage controlled oscillator with common mode adjustment start-up
US-9083349-B1 · Jul 14, 2015 · US
US10425038B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10425038-B2 |
| Application number | US-201615262003-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 11, 2016 |
| Priority date | Oct 14, 2015 |
| Publication date | Sep 24, 2019 |
| Grant date | Sep 24, 2019 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.
Opening claim text (preview).
What is claimed is: 1. An oscillator for generating oscillation signals at two output terminals, comprising: an inductor coupled between the two output terminals; a capacitor coupled between the two output terminals; two P-type transistors, wherein source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively; and two N-type transistors, wherein gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are directly connected to drain electrodes of the two P-type transistors, respectively; wherein the drain electrodes of the two N-type transistors are directly connected to two internal nodes of the inductor; and the capacitor and a portion of the inductor form a low-pass filter for filtering an unwanted frequency component. 2. The oscillator of claim 1 , wherein the unwanted frequency component is generated according to another portion of the inductor and a parasitic capacitance. 3. The oscillator of claim 1 , further comprising: a first auxiliary capacitor, coupled between one of the two output terminals and the drain electrode of one of the two N-type transistors. 4. The oscillator of claim 3 , wherein the capacitor, the first auxiliary capacitor and a portion of the inductor form a low-pass filter to filter an unwanted frequency component. 5. The oscillator of claim 4 , wherein the unwanted frequency component is generated according to another portion of the inductor and a parasitic capacitance. 6. The oscillator of claim 5 , wherein α*L*C PAR =(1-α)*L*C RES , (α*L) is an inductance of the another portion of the inductor, C PAR is the parasitic capacitance, ((1-α)*L) is an inductance of the portion of the inductor, and C RES is a capacitance of the first auxiliary capacitor. 7. The oscillator of claim 4 , further comprising: a second auxiliary capacitor, coupled between another one of the two output terminals and the drain electrode of another one of the two N-type transistors. 8. An oscillator for generating oscillation signals at two output terminals, comprising: an inductor coupled between the two output terminals; a capacitor coupled between the two output terminals; two P-type transistors, wherein source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively; and two N-type transistors, wherein gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are directly connected to drain electrodes of the two P-type transistors, respectively; wherein the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor; a switch module, coupled between the drain electrodes of two N-type transistors and the two internal nodes of the inductor, for selectively connecting the drain electrodes of two N-type transistors to the two internal nodes of the inductor or not; wherein the switch module further selectively connects the drain electrodes of two N-type transistors to other two internal nodes of the inductor or not. 9. The oscillator of claim 8 , wherein when the oscillator operates in a first mode, the switch module connects the drain electrodes of two N-type transistors to the two internal nodes of the inductor, and not connect the drain electrodes of two N-type transistors to the other two internal nodes of the inductor; and when the oscillator operates in a second mode, the switch module connects the drain electrodes of two N-type transistors to the other two internal nodes of the inductor, and not connect the drain electrodes of two N-type transistors to the two internal nodes of the inductor. 10. The oscillator of claim 9 , wherein the first mode is a Long Term Evolution (LTE) mode, and the second mode is a 2G mode. 11. The oscillator of claim 1 , further comprising: a plurality of gating transistors connected in parallel with the two P-type transistors and the two N-type transistors, respectively, for providing additional current to adjust a transconductance of the oscillator. 12. The oscillator of claim 11 , wherein the oscillator operates in a first mode, the gating transistors are turned off; and when the oscillator operates in a second mode, the gating transistors are turned on. 13. The oscillator of claim 12 , wherein the first mode is a Long Term Evolution (LTE) mode, and the second mode is a 2G mode. 14. The oscillator of claim 1 , wherein the oscillator is a digitally controlled oscillator (DCO) or a voltage-controlled oscillator (VCO). 15. An oscillator for generating oscillation signals at two output terminals, comprising: two P-type transistors, wherein source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively; two N-type transistors, wherein gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively; and a low-pass filter, coupled to the two P-type transistors and the two N-type transistors, for filtering a frequency component of the oscillation signals generated according to a first inductor and a parasitic capacitance; wherein the low-pass filter is formed by a second inductor and a capacitor, and the second inductor is different from the first inductor. 16. The oscillator of claim 15 , wherein the low-pass filter is an inductor-capacitor filter. 17. The oscillator of claim 15 , wherein a desired frequency component of the oscillation signals is generated according to the first inductor, the second inductor and the capacitor. 18. An oscillator for generating oscillation signals at two output terminals, comprising: an inductor coupled between the two output terminals; a capacitor coupled between the two output terminals; two first transistors, wherein each of the first transistors has a first electrode, a second electrode and a gate electrode, the first electrodes of the two first transistors are coupled to a supply voltage, and the gate electrodes of the two first transistors are coupled to the two output terminals, respectively; and two second transistors, wherein each of the second transistors has a first electrode, a second electrode and a gate electrode, the gate electrodes of the two second transistors are coupled to the two output terminals, respectively, and the first electrodes of the two second transistors are directly connected to the second electrodes of the two first transistors, respectively; wherein the first electrodes of the two second transistors are directly connected to two internal nodes of the inductor; and the capacitor and a portion of the inductor form a low-pass filter for filtering an unwanted frequency component. 19. The oscillator of claim 18 , wherein the unwanted frequency component is generated according to another portion of the inductor and a parasitic capacitance. 20. An oscillator for generating oscillation signals at two output terminals, comprising: an inductor coupled between the two output terminals; a capacitor coupled between the two output terminals; two first transistors, wherein
Lowering the supply voltage and saving power · CPC title
the means comprising switched elements · CPC title
the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair · CPC title
the amplifier comprising one or more field effect transistors · CPC title
switched inductors · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.