Bidirectional AC/DC H-bridge power converter

Patent metadata

Field	Value
Publication number	US-10425014-B2
Application number	US-201815866403-A
Country	US
Kind code	B2
Filing date	Jan 9, 2018
Priority date	Jan 10, 2017
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

An AC/DC converter including: an H bridge; an inductance in series with an input of the bridge; an inductance in series with an output of the bridge; and a circuit capable of controlling the bridge alternately to a first configuration where first and second diagonals of the bridge are respectively conductive and non-conductive, and to a second complementary configuration, the circuit being capable, during a phase of transition between the first and second configurations, of: turning on a first switch of the second diagonal; turning off a first switch of the first diagonal when the current flowing through this switch takes a zero value; turning on the second switch of the second diagonal; and turning off the second switch of the first diagonal when the current flowing through this switch takes a zero value.

First claim

What is claimed is:

1. An AC-voltage-to-DC-voltage conversion circuit, comprising:
four first bidirectional switches forming a first H bridge, first and second input nodes of the first H bridge being respectively coupled to first and second nodes of application of the AC voltage;
a transformer comprising a primary winding and a secondary winding, magnetically coupled, first and second ends of the primary winding being respectively coupled to first and second output nodes of the first H bridge;
a first inductance series-connected with the first H bridge between the first input node of the first H bridge and the first node of application of the AC voltage;
a second inductance series-connected with the first H bridge, between the first output node of the first H bridge and the first end of the primary winding; and
a control circuit configured to control the first H bridge alternately to a first configuration where the switches of a first diagonal of the first H bridge are on and the switches of a second diagonal of the first H bridge are off, and to a second configuration where the switches of the first diagonal are off and the switches of the second diagonal are on,
the control circuit being configured to, during a phase of transition between the first and second configurations, successively:
turn on a first switch of the second diagonal while holding first and second switches of the first diagonal in an on state and a second switch of the second diagonal in an off state;
turn off the first switch of the first diagonal when the current flowing through this switch takes a zero value;
turn on the second switch of the second diagonal, while holding the first switch of the second diagonal and the second switch of the first diagonal in the on state and the first switch of the first diagonal in the off state; and
turn off the second switch of the first diagonal when the current flowing through this switch takes a zero value.

2. The conversion circuit of claim 1 , further comprising four second switches forming a second H bridge, first and second input nodes of the second H bridge being respectively coupled to first and second ends of the secondary winding of the transformer, and first and second output nodes of the second bridge being respectively coupled to first and second DC voltage supply nodes.

3. The conversion circuit of claim 2 , wherein the control circuit is configured to control the second H bridge alternately to a first configuration where the switches of a first diagonal of the second H bridge are on and the switches of a second diagonal of the second H bridge are off, and to a second configuration where the switches of the first diagonal are off and the switches of the second diagonal are on.

4. The conversion circuit of claim 3 , wherein the control circuit is configured to switch the first H bridge between its first and second configurations and to switch the second H bridge between its first and second configurations substantially at the same frequency.

5. The conversion circuit of claim 1 , wherein the control circuit is configured to switch the first H bridge between the first and second configurations at a frequency greater than or equal to 1 MHz.

6. The conversion circuit of claim 1 , wherein the control circuit is further configured to turn on each first switch, and to automatically turn off each first switch when a current flowing therethrough takes a zero value.

7. The conversion circuit of claim 1 , wherein each first switch is equivalent to an anti-series association of first and second MOS transistors connected at first and second respective drains of the first and second transistors, with sources of the first and second transistors respectively forming conduction nodes of the switch, and gates of the first and second MOS transistors forming first and second switch control nodes.

8. The conversion circuit of claim 7 , wherein the control circuit is configured to, when turning on a switch of the first H bridge, apply a turn-on control signal to a gate of one of the first and second transistors of the switch, and hold a blocking signal on the gate of the other transistor.

9. The conversion circuit of claim 8 , wherein the control circuit is configured to, when -turning on a switch of the first H bridge, apply a turn-on control signal to a gate of the first transistor and a turn-off signal to a gate of the second transistor when a current to be conducted by the switch has a first biasing, and apply a turn-on control signal to the gate of the second transistor and a turn-off signal to the gate of the first transistor when the current to be conducted by the switch has a second biasing opposite to the first biasing.

10. The conversion circuit of claim 1 , wherein the control circuit comprises, for each first switch:
a first circuit configured to detect that a current in the first switch has taken a zero value and to supply a logic output signal corresponding to a result of this detection;
a second circuit configured to perform a logic operation between the signal supplied by the first circuit and an external switch control signal, and to supply a logic switch control signal corresponding to a result of this operation.

11. The conversion circuit of claim 10 , wherein, for each first switch, the first circuit of the control circuit comprises a current measurement device configured to measure a current flowing through the switch and a comparator configured to compare an output signal of the current measurement device with a reference signal.

12. The conversion circuit of claim 11 , wherein, for each first switch, the second circuit of the control circuit comprises first and second D flip-flops each comprising first, second, and third input nodes, and an output node, each D flip-flop configured to:
copy, on each rising edge of a binary signal applied to the second input node, a binary signal applied to the first input node on the output node when a binary signal in a first state is applied to the third input node;
force a binary signal supplied on the output node to a predetermined state, independently from a state of the binary signals applied to the first and second input nodes, when a binary signal in a second state is applied to the third input node.

13. The conversion circuit of claim 12 , wherein, for each first switch:
the first input node of each D flip-flop is coupled to a node of application of a fixed binary signal in a first state;
the third input node of each D flip-flop is coupled to a node of application of the external switch control signal; and
the second input node of the first D flip-flop is coupled to an output of the comparator, and the second input node of the second D flip-flop is coupled to the output of the comparator via an inverter.

14. The conversion circuit of claim 13 , wherein, for each first switch, the second circuit of the control circuit comprises an AND gate having a first input coupled to the output node of the first D flip-flop, a second input coupled to the output node of the second D flip-flop, and an output coupled to a node for supplying the logic output signal of the second circuit.

15. The conversion circuit of claim 1 , wherein the first switches are gallium nitride switches.

16. The conversion circuit of claim 1 , wherein the control circuit being configured to, during a phase of transition between the first and second configurations, successively:
turn on a first switch of the second diagonal while maintaining the second switch of the second diagonal off;
turn off a first switch of the first diagonal when the current flowing thro

Assignees

• Commissariat Energie Atomique

Inventors

• Sterna Léo
• Ladhari Othman
• Ferrieux Jean-Paul
• Frey David
• Jeannin Pierre-Olivier

Classifications

• H02M7/4807

  having a high frequency intermediate AC stage · CPC title

• H02M7/1626

  with automatic control of the output voltage or current · CPC title

• H02M7/5388

  with asymmetrical configuration of switches · CPC title

• H03K3/35625

  using complementary field-effect transistors · CPC title

• H02M1/4258

  using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage (H02M1/4241 takes precedence) · CPC title