Interconnect structure and method for on-chip information transfer

Patent metadata

Field	Value
Publication number	US-10424733-B2
Application number	US-201715820627-A
Country	US
Kind code	B2
Filing date	Nov 22, 2017
Priority date	Nov 25, 2016
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

An interconnect structure for on-chip information transfer, and a method for on-chip information transfer. The interconnect structure comprises a source configured for electrically generating plasmons; a detector configured for electrically detecting the generated plasmons; and a plasmonic waveguide coupled between the source and the detector.

First claim

What is claimed is:

1. An interconnect structure for on-chip information transfer, comprising:
a source configured for electrically generating plasmons;
a detector configured for electrically detecting the generated plasmons; and
a plasmonic waveguide coupled between the source and the detector;
wherein the source or the detector comprise a metal-insulator-metal (MIM) junction for electrically generating the plasmons or for electrically detecting the generated plasmons, respectively.

2. The interconnect structure of claim 1 , wherein the MIM junction is configured for generating the plasmons via bias induced tunneling.

3. The interconnect structure of claim 1 , wherein the MIM junction is configured for detecting the generated plasmons via a modified tunnel-current under bias induced tunneling.

4. The interconnect structure of claim 1 , wherein the plasmonic waveguide comprises a first portion configured for propagating surface plasmon polaritons (SPPs) excited in the source.

5. The interconnect structure of claim 4 , wherein the plasmonic waveguide comprises a second portion configured for coupling the SPPs to a long range SPP (LRSPP) mode of the second portion and propagation of LRSPPs.

6. The interconnect structure of claim 5 , wherein the second portion of the plasmonic waveguide comprises two sections separated by a gap configured for electrical isolation of the source and detector while preserving the propagation of the LRSPPs.

7. The interconnect structure of claim 6 , wherein the second portion of the plasmonic waveguide has a smaller thickness than the first portion.

8. The interconnect structure of claim 6 , wherein the plasmonic waveguide comprises a third portion configured for coupling the LRSPPs to an SPP mode of the third portion for detection of the SPPs in the detector.

9. The interconnect structure of claim 8 , wherein the third portion of the plasmonic waveguide has a larger thickness than the second portion.

10. The interconnect structure of claim 1 , wherein the plasmonic waveguide comprises a insulator-metal-insulator (IMI) plasmonic waveguide.

11. The interconnect structure of claim 1 , wherein the plasmonic waveguide has a length of up to about 1 mm, preferably in the range from about 100 μm to 1 mm.

12. The interconnect structure of claim 1 , wherein the source, the detector and the plasmonic waveguide are formed on the same substrate.

13. A method for on-chip information transfer, the method comprising the steps of:
providing the interconnect structure of claim 1 ;
electrically generating plasmons using the interconnect structure;
electrically detecting the generated plasmons using the interconnect structure; and
propagating the plasmons in the plasmonic waveguide coupled between the source and the detector using the interconnect structure.

14. The method of claim 13 , comprising generating the plasmons via bias induced tunneling.

15. The method of claim 13 , comprising detecting the generated plasmons via a modified tunnel-current under bias induced tunneling.

16. The method of claim 13 , comprising propagating surface plasmon polaritons (SPPs) excited in the source in a first portion of plasmonic waveguide.

17. The method of claim 11 , comprising coupling the SPPs to a long range SPP (LRSPP) mode of a second portion of the plasmonic waveguide and propagating the LRSPPs.

18. The method of claim 12 , comprising providing a gap in the second portion of the plasmonic waveguide for electrical isolation of the source and detector while preserving the propagation of the LRSPPs, preferably comprising coupling the LRSPPs to an SPP mode of a third portion of the plasmonic waveguide for detection of the SPPs in the detector.

19. An interconnect structure for on-chip information transfer, comprising:
a source configured for electrically generating plasmons;
a detector configured for electrically detecting the generated plasmons; and
a plasmonic waveguide coupled between the source and the detector;
wherein the plasmonic waveguide comprises a first portion configured for propagating surface plasmon polaritons (SPPs) excited in the source and a second portion configured for coupling the SPPs to a long range SPP (LRSPP) mode of the second portion and propagation of LRSPPs.

20. A method for on-chip information transfer, the method comprising the steps of:
providing the interconnect structure of claim 19 ;
electrically generating plasmons using the interconnect structure;
electrically detecting the generated plasmons using the interconnect structure; and
propagating the plasmons in the plasmonic waveguide coupled between the source and the detector using the interconnect structure.

21. The method of claim 20 , comprising generating the plasmons via bias induced tunneling.

22. The method of claim 20 , comprising detecting the generated plasmons via a modified tunnel-current under bias induced tunneling.

23. The method of claim 20 , comprising propagating surface plasmon polaritons (SPPs) excited in the source in a first portion of plasmonic waveguide.

24. The method of claim 23 , comprising coupling the SPPs to a long range SPP (LRSPP) mode of a second portion of the plasmonic waveguide and propagating the LRSPPs.

25. The method of claim 24 , comprising providing a gap in the second portion of the plasmonic waveguide for electrical isolation of the source and detector while preserving the propagation of the LRSPPs, preferably comprising coupling the LRSPPs to an SPP mode of a third portion of the plasmonic waveguide for detection of the SPPs in the detector.

26. An interconnect structure for on-chip information transfer, comprising:
a source configured for electrically generating plasmons;
a detector configured for electrically detecting the generated plasmons; and
a plasmonic waveguide coupled between the source and the detector;
wherein the plasmonic waveguide comprises an insulator-metal-insulator (IMI) plasmonic waveguide.

27. A method for on-chip information transfer, the method comprising the steps of:
providing the interconnect structure of claim 26 ;
electrically generating plasmons using the interconnect structure;
electrically detecting the generated plasmons using the interconnect structure; and
propagating the plasmons in the plasmonic waveguide coupled between the source and the detector using the interconnect structure.

28. The method of claim 27 , comprising generating the plasmons via bias induced tunneling.

29. The method of claim 27 , comprising detecting the generated plasmons via a modified tunnel-current under bias induced tunneling.

30. The method of claim 27 , comprising propagating surface plasmon polaritons (SPPs) excited in the source in a first portion of plasmonic waveguide.

31. The method of claim 30 , comprising coupling the SPPs to a long range SPP (LRSPP) mode of a second portion of the plasmonic waveguide and propagating the LRSPPs.

32. The method of claim 31 , comprising providing a gap in the second portion of the plasmonic waveguide for electrical isolation of the source and detector while preserving the propagation of the LRSPPs, preferably comprising coupling the LRSPPs to an SPP mode of a third portion of the plasmonic waveguide for detection of the SPPs in the detector.

33. An

Assignees

• Nat Univ Singapore

Inventors

• Du Wei
• Wang Tao
• Nijhuis Christian Albertus

Classifications

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• G02B6/1226 Primary

  involving surface plasmon interaction · CPC title

• H01L28/40

  Electricity · mapped topic