Array substrate, manufacturing method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-10424604-B2
Application number	US-201615529495-A
Country	US
Kind code	B2
Filing date	Nov 7, 2016
Priority date	Mar 31, 2016
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

The present disclosure provides an array substrate, its manufacturing method, and a display apparatus containing the array substrate. The array substrate includes: a substrate; a plurality of gate lines and a plurality of data lines, disposed over the substrate and arranged in rows and columns respectively; and a plurality of pixel regions, each arranged in an area defined by crossing gate lines and data lines and comprising a pixel electrode. The plurality of data lines are configured such that in each pixel region, orthographic projection of any one of the plurality of data lines on the substrate and orthographic projection of a corresponding pixel electrode on the substrate has an overlapping area having a width of ≥0 μm.

First claim

The invention claimed is:

1. An array substrate, comprising:
a substrate;
a plurality of gate lines and a plurality of data lines, disposed over the substrate and arranged in rows and columns respectively; and
a plurality of pixel regions, each arranged in an area defined by crossing gate lines and data lines and comprising a pixel electrode;
wherein:
the plurality of data lines are configured such that in each pixel region, orthographic projection of any one of the plurality of data lines on the substrate and orthographic projection of a corresponding pixel electrode on the substrate has an overlapping area having a width of ≥0 μm;

the array substrate further comprises:
a shielding layer, disposed over, and configured to reduce or prevent light leakage from, a periphery of each pixel region; and
a plurality of thin-film transistors, each arranged in one of the plurality of pixel regions and comprising a gate electrode,
the gate electrode, the shielding layer and the plurality of gate lines are disposed in a same gate metal layer and comprise a same composition;
each thin-film transistor further comprises:
a drain electrode, wherein the drain electrode and the shielding layer are configured to substantially contribute to a storage capacitance of the pixel in each pixel region; and
a passivation layer,

the passivation layer is disposed between, and configured to insulate, the drain electrode and the pixel electrode in each pixel region;
the passivation layer is provided a via, configured to electrically couple the pixel electrode with the drain electrode therethrough;
the passivation layer comprises at least one organic insulating layer;
in each pixel region, the storage capacitance comprises a first storage capacitor and a second storage capacitor;
a portion of the drain electrode corresponding to the via is disposed to directly face the shielding layer to thereby form the first storage capacitor; and
the pixel electrode and the shielding layer are configured to form the second storage capacitor.

2. The array substrate of claim 1 , further comprising at least one organic insulating layer, disposed between any one of the plurality of data lines and the corresponding pixel electrode in each pixel region.

3. The array substrate of claim 1 , wherein in each pixel region, orthographic projection of the shielding layer on the substrate overlaps with a gap between orthographic projection of any of the plurality of gate lines and orthographic projection of the pixel electrode.

4. The array substrate of claim 1 , wherein two of the plurality of gate lines are arranged between every two adjacent rows of pixel regions, and two columns of pixel regions are arranged between every two adjacent data lines.

5. The array substrate of claim 4 , wherein each of the plurality of data lines comprises a first portion, disposed over a first gap between two adjacent pixel regions, and configured such that a width of the first portion of the each data line is substantially equal to, or more than, a width of the first gap between the two adjacent pixel regions.

6. The array substrate of claim 5 , wherein the shielding layer comprises a second portion, disposed over a second gap between two neighboring pixel regions arranged between two adjacent data lines of the plurality of data lines, and configured such that a width of the second portion of the shielding layer is substantially equal to, or more than, a width of the second gap between the two neighboring pixel regions.

7. The array substrate of claim 1 , wherein the width of the overlapping area is ranged about 2-3.5 μm.

8. The array substrate of claim 1 , wherein the shielding layer is electrically coupled to a common electrode.

9. The array substrate of claim 1 , wherein each of the plurality of thin-film transistors further comprises a gate insulating layer, disposed over the gate metal layer and comprising at least one organic insulating layer.

10. A display apparatus, comprising an array substrate according to claim 1 .

11. A method for fabricating the array substrate of claim 1 , the method comprising:
forming the plurality of gate lines over the substrate;
forming the plurality of data lines, wherein the plurality of gate lines and the plurality of data lines cross one another to define a plurality of areas for arranging each of a plurality of pixel regions therein; and
forming the pixel electrode in each of the plurality of pixel regions.

12. The method according to claim 11 , wherein the forming the plurality of gate lines over the substrate comprises:
forming the plurality of gate lines and the shielding layer over a substrate.

13. The method according to claim 12 , wherein:
the array substrate comprises the plurality of thin-film transistors, each disposed in each pixel region and comprising a gate electrode, a drain electrode, and a source electrode; and
the forming the plurality of gate lines over the substrate comprises:
forming the gate electrode and the shielding layer and the plurality of gate lines by patterning over a gate metal layer.

14. The method according to claim 13 , further comprising, between the forming a plurality of gate lines over a substrate and the forming a plurality of data lines:
forming a gate insulating layer over the gate electrode and the shielding layer and the plurality of gate lines, wherein the gate insulating layer comprises at least one organic insulating layer.

15. The method according to claim 13 , further comprising, between the forming the plurality of data lines and the forming the pixel electrode in each of the plurality of pixel regions:
forming the drain electrode and a passivation layer in each pixel region, wherein the passivation layer comprises an organic insulating layer and is provided with a via, and the pixel electrode is electrically coupled with the drain electrode through the via.

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Rui
• Qiu Haijun
• Shang Fei
• Kim Jaikwang
• Li Shaoru
• Xu Zhuo

Classifications

• G02F2201/123

  pixel · CPC title

• G02F1/133512

  Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136213

  Storage capacitors associated with the pixel electrode · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title