Semiconductor devices having modulated nanowire counts

Patent metadata

Field	Value
Publication number	US-10424580-B2
Application number	US-201113996505-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a first semiconductor device comprising a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire; and
a second semiconductor device comprising one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire, the second semiconductor device comprising one or more fewer nanowires than the first semiconductor device, and the first and second uppermost nanowires disposed in a same plane orthogonal to the first and second vertical planes.

2. The semiconductor structure of claim 1 , wherein each of the nanowires comprises a discrete channel region.

3. The semiconductor structure of claim 2 , wherein each of the nanowires comprises a pair of discrete source and drain regions.

4. The semiconductor structure of claim 2 , wherein the plurality of nanowires of the first semiconductor device comprises a first pair of non-discrete source and drain regions, and the one or more nanowires of the second semiconductor device comprises a second pair of non-discrete source and drain regions.

5. The semiconductor structure of claim 1 , further comprising:
an intervening dielectric layer disposed between the substrate and the first and second semiconductor devices, the intervening dielectric layer thicker between the substrate and the second semiconductor device than between the substrate and the first semiconductor device.

6. The semiconductor structure of claim 1 , wherein the first semiconductor device further comprises a first gate electrode stack surrounding a portion of each of the plurality of nanowires, and the second semiconductor device further comprises a second gate electrode stack surrounding a portion of each of the one or more nanowires.

7. The semiconductor structure of claim 6 , wherein the first and second gate electrode stacks each comprise a high-K gate dielectric layer and a metal gate electrode layer.

8. The semiconductor structure of claim 1 , wherein each of the nanowires consists essentially of silicon, and the first and second semiconductor devices are NMOS devices.

9. The semiconductor structure of claim 1 , wherein each of the nanowires consists essentially of silicon germanium, and the first and second semiconductor devices are PMOS devices.

10. The semiconductor structure of claim 1 , wherein the first and second vertical planes are parallel to one another.

11. The semiconductor structure of claim 6 , wherein the first semiconductor device further comprises first and second contacts surrounding respective portions of each of the plurality of nanowires, and the second semiconductor device further comprises third and fourth contacts surrounding respective portions of each of the one or more nanowires.

12. The semiconductor structure of claim 11 , wherein the first semiconductor device further comprises first and second spacers disposed between the first gate electrode stack and the first and second contacts, respectively, and wherein the second semiconductor device further comprises third and fourth spacers disposed between the second gate electrode stack and the third and fourth contacts, respectively.

13. A semiconductor structure, comprising:
a first semiconductor device comprising a first plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire;
a second semiconductor device comprising a second plurality of nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire, the second semiconductor device comprising one or more fewer nanowires than the first semiconductor device; and
a third semiconductor device comprising one or more nanowires disposed above the substrate and stacked in a third vertical plane with a third uppermost nanowire, the third semiconductor device comprising one or more fewer nanowires than the second semiconductor device, and the first, second and third uppermost nanowires disposed in a same plane orthogonal to the first, second and third vertical planes.

14. The semiconductor structure of claim 13 , wherein each of the nanowires comprises a discrete channel region.

15. The semiconductor structure of claim 14 , wherein each of the nanowires comprises a pair of discrete source and drain regions.

16. The semiconductor structure of claim 14 , wherein the first plurality of nanowires of the first semiconductor device comprises a first pair of non-discrete source and drain regions, the second plurality of nanowires of the second semiconductor device comprises a second pair of non-discrete source and drain regions, and the one or more nanowires of the third semiconductor device comprises a third pair of non-discrete source and drain regions.

17. The semiconductor structure of claim 13 , further comprising:
an intervening dielectric layer disposed between the substrate and the first, second and third semiconductor devices, the intervening dielectric layer thicker between the substrate and the third semiconductor device than between the substrate and the first and second semiconductor devices, and thicker between the substrate and the second semiconductor device than between the substrate and the first semiconductor device.

18. The semiconductor structure of claim 13 , wherein the first semiconductor device further comprises a first gate electrode stack surrounding a portion of each of the first plurality of nanowires, the second semiconductor device further comprises a second gate electrode stack surrounding a portion of each of the second plurality of nanowires, and the third semiconductor device further comprises a third gate electrode stack surrounding a portion of each of the one or more nanowires.

19. The semiconductor structure of claim 18 , wherein the first, second and third gate electrode stacks each comprise a high-K gate dielectric layer and a metal gate electrode layer.

20. The semiconductor structure of claim 13 , wherein each of the nanowires consists essentially of silicon, and the first, second and third semiconductor devices are NMOS devices.

21. The semiconductor structure of claim 13 , wherein each of the nanowires consists essentially of silicon germanium, and the first, second and third semiconductor devices are PMOS devices.

22. The semiconductor structure of claim 13 , wherein the first, second and third vertical planes are parallel to one another.

23. The semiconductor structure of claim 18 , wherein the first semiconductor device further comprises first and second contacts surrounding respective portions of each of the first plurality of nanowires, the second semiconductor device further comprises third and fourth contacts surrounding respective portions of each of the second plurality of nanowires, and the third semiconductor device further comprises fifth and sixth contacts surrounding respective portions of each of the one or more nanowires.

24. The semiconductor structure of claim 23 , wherein the first semiconductor device further comprises first and second spacers disposed between the first gate electrode stack and the first and second contacts, respectively, wherein the second semiconductor device further comprises third and fourth spacers disposed between the second gate electrode stack and the third and fourth contacts, respectively, and wherein the third semiconductor device further comprises

Assignees

• Cappellani Annalisa
• Kuhn Kelin J
• Rios Rafael
• Bhimarasetti Gopinath
• Ghani Tahir
• Kim Seiyon
• Intel Corp

Inventors

• Cappellani Annalisa
• Kuhn Kelin J
• Rios Rafael
• Bhimarasetti Gopinath
• Ghani Tahir
• Kim Seiyon

Classifications

• H10P14/3451

  Structure · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• B82Y99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H01L29/66439

  Electricity · mapped topic