Method for manufacturing a dual work function semiconductor device and the semiconductor device made thereof

Patent metadata

Field	Value
Publication number	US-10424517-B2
Application number	US-201615180313-A
Country	US
Kind code	B2
Filing date	Jun 13, 2016
Priority date	Jan 9, 2009
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A method for manufacturing a dual work function semiconductor device includes forming a first silicon oxide layer on a substrate and forming a first hafnium-containing dielectric material layer on the first silicon oxide layer. The method further includes forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer and performing a thermal treatment to intermix the silicon oxide layer, the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layers. This results in an intermixing dielectric layer containing hafnium, aluminum, silicon, and oxygen. The method further includes forming a first metal-containing conductive layer on the intermixing dielectric layer and patterning the first metal-containing conductive layer and the intermixing dielectric layer, thereby forming a first gate stack in a first region.

First claim

What is claimed is:

1. A method, comprising:
receiving a substrate having an insulating feature, the substrate having a first region and a second region separated by the insulating feature,
forming a first gate stack having a first work function on the substrate within the first region, wherein forming of the first gate stack includes:
forming a first hafnium-containing dielectric material layer on the substrate,
forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer,
performing a thermal treatment to intermix the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layer while the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layer cover the insulating feature and continuously extend from the first region to the second region over the insulating feature, resulting in an intermixing dielectric layer,
after the thermal treatment, forming a first metal-containing conductive layer on the intermixing dielectric layer, and
patterning the intermixing dielectric layer and the first metal-containing conductive layer, thereby forming the first gate stack in the first region; and

after forming the first gate stack, forming a second gate stack having a second work function less than the first work function on the substrate, wherein forming of the second gate stack includes:
forming a second hafnium-containing dielectric material layer,
forming a lanthanum-containing dielectric material layer on the second hafnium-containing dielectric material layer,
forming a second metal-containing conductive layer on the lanthanum-containing dielectric material layer, and
patterning the second hafnium-containing dielectric material layer, the lanthanum-containing dielectric material layer and the second metal-containing conductive layer, thereby forming the second gate stack in the second region.

2. The method of claim 1 , wherein the thermal treatment is selected to increase the first work function and decrease an equivalent oxide thickness (EOT) of the intermixing dielectric layer.

3. The method of claim 2 , wherein the thermal treatment is selected such that the first work function of the first gate stack is tuned to a range between 4.7 eV and 5.2 eV.

4. The method of claim 2 , wherein the thermal treatment is selected such that an EOT of a gate dielectric layer of the first gate stack is tuned to be less than 2 nm, and wherein the gate dielectric layer includes the intermixing dielectric layer.

5. The method of claim 1 , wherein the thermal treatment is performed in an ambient with at least one of argon and nitrogen.

6. The method of claim 1 , wherein the thermal treatment is performed at a temperature range between 800 degrees Celsius and 1300 degrees Celsius and during a time period ranging between 0.1 second and 30 seconds.

7. The method of claim 1 , further comprising performing a spike annealing at a temperature of at least 1035 degrees Celsius after the thermal treatment.

8. The method of claim 1 , further comprising:
forming a silicon oxide layer between the substrate and the first hafnium-containing dielectric material layer.

9. The method of claim 8 , wherein the thermal treatment intermixes the silicon oxide layer, the hafnium-containing dielectric material layer and the aluminum-containing dielectric material layer to form the intermixing dielectric layer containing hafnium, aluminum, silicon and oxygen.

10. The method of claim 1 , wherein
the first metal-containing conductive layer includes a first metal-containing conductive material selected from nickel (Ni), ruthenium oxide (RuO), and molybdenum nitride (MoN); and
the second metal-containing conductive layer includes a second metal-containing conductive material selected from ruthenium (Ru), zirconium (Zr), niobium (Nb), tantalum (Ta), and titanium silicide (TiSi 2 ).

11. The method of claim 1 , wherein the performing of the thermal treatment causes regrowth while the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layer are overlapped with and covering the insulating feature.

12. A method, comprising:
receiving a substrate having an insulating feature, the substrate having a first region and a second region separated by the insulating feature;
forming a first silicon oxide layer on the substrate;
forming a first hafnium-containing dielectric material layer on the first silicon oxide layer;
forming an aluminum-containing dielectric material layer on the first hafnium-containing dielectric material layer;
performing a thermal treatment to intermix the first silicon oxide layer, the first hafnium-containing dielectric material layer and the aluminum-containing dielectric material layer while the first silicon oxide layer, the first hafnium-containing dielectric material layer, and the aluminum-containing dielectric material layer cover the insulating feature and continuously extend from the first region to the second region over the insulating feature, resulting in an intermixing dielectric layer containing hafnium, aluminum, silicon, and oxygen;
forming a first metal-containing conductive layer on the intermixing dielectric layer;
patterning the first metal-containing conductive layer and the intermixing dielectric layer, thereby forming a first gate stack in the first region; and
forming a second gate stack in the second region.

13. The method of claim 12 , wherein forming of the second gate stack further includes:
forming a second silicon oxide layer on the substrate and on the first gate stack;
forming a second hafnium-containing dielectric material layer on the second silicon oxide layer;
forming a lanthanum-containing dielectric material layer on the second hafnium-containing dielectric material layer,
forming a second metal-containing conductive layer on the lanthanum-containing dielectric material layer, and
patterning the second silicon oxide layer, the second hafnium-containing dielectric material layer, the lanthanum-containing dielectric material layer and the second metal-containing conductive layer, thereby forming the second gate stack in the second region, wherein the first gate stack has a first work function and the second gate stack has a second work function less than the first work function.

14. The method of claim 12 , wherein the thermal treatment is designed to tune the first work function to a range between 4.7 eV and 5.2 eV, and to adjust an equivalent oxide thickness (EOT) of the intermixing dielectric layer to be less than 2 nm.

15. The method of claim 12 , further comprising performing a spike annealing process at a temperature of at least 1035 degrees Celsius after the thermal treatment.

16. The method of claim 12 , wherein
the first metal-containing conductive layer includes a first metal-containing conductive material selected from nickel (Ni), ruthenium oxide (RuO), and molybdenum nitride (MoN); and
the second metal-containing conductive layer includes a second metal-containing conductive material selected from ruthenium (Ru), zirconium (Zr), niobium (Nb), tantalum (Ta), and titanium silicide (TiSi 2 ).

17. A method, comprising:
receiving a substrate having an insulating feature, the substrate having a first region and a second region separated by the insulating feature;
forming a first gate stack having a first work function on the substrate within the first region, wherein forming of the first gate stack includes:
forming a first silicon oxide layer on t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tseng Joshua
• Okuno Yasutoshi
• Ragnarsson Lars-Ake
• Schram Tom
• Kubicek Stefan
• Hoffman Thomas Y
• Sengoku Naohisa

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D84/8314

  the IGFETs characterised by having gate insulating layers with different properties · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title