Interconnection structure having a via structure and fabrication thereof

Patent metadata

Field	Value
Publication number	US-10424508-B2
Application number	US-201514748811-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Nov 13, 2012
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.

First claim

What is claimed is:

1. A method of forming an interconnection structure comprising:
providing a substrate having a first side and a second side opposite to the first side;
forming at least one electric device on the substrate, wherein the at least one electric device comprises a plurality of metal electrodes;
forming a via hole through one of the plurality of the metal electrodes of the electric device and the substrate, wherein the via hole has a first opening neighboring the first side and a second opening neighboring the second side;
forming a first pad covering the first opening and directly on the at least one electric device, wherein a portion of the at least one electric device is between the first pad and the substrate; and
forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad, and the via structure exceeds the second opening.

2. The method of forming an interconnection structure as claimed in claim 1 , further comprising:
forming a photosensitive layer on the substrate covering the at least one electric device prior to forming the via hole.

3. The method of forming an interconnection structure as claimed in claim 1 , further comprising forming an insulating layer surrounding a sidewall of the via hole prior to forming the via structure.

4. The method of forming an interconnection structure as claimed in claim 1 , wherein forming the first pad comprises performing a first metal screen printing process to form the first pad covering the first opening.

5. The method of forming an interconnection structure as claimed in claim 1 , further comprising forming a second pad covering the via hole subsequent to forming the via structure.

6. The method of forming an interconnection structure as claimed in claim 1 , wherein forming the via hole through the substrate comprises drilling the via hole through the substrate with a laser beam.

7. The method of forming an interconnection structure as claimed in claim 1 , wherein forming the via structure is performed by electric plating using the first pad as a seed layer.

8. The method for forming an interconnection structure as claimed in claim 1 , wherein the metal electrode of the electric device being through by the via hole is a drain electrode.

9. A method for forming an interconnection structure, comprising:
providing a substrate having a first side a second side opposite to the first side;
forming at least one electric device on the substrate, wherein the at least one electric device comprises a plurality of metal electrodes;
forming a via hole through one of the plurality of the metal electrodes of the electric device and the substrate, wherein the via hole has a first opening neighboring the first side and a second opening neighboring the second side; and
performing a screen printing process on the first side to fill a conductive material into the via hole so as to form a via structure in the via hole and a first pad disposed on the first side and directly on the at least one electric device, adjoined to the via structure, and the via structure exceeds the second opening, wherein a portion of the at least one electric device is between the first pad and the substrate.

10. The method for forming an interconnection structure as claimed in claim 9 , further comprising:
forming a photosensitive layer on the substrate covering the at least one electric device prior to forming the via hole.

11. The method for forming an interconnection structure as claimed in claim 9 , further comprising forming an insulating layer surrounding a sidewall of the via hole prior to forming the via structure.

12. The method for forming an interconnection structure as claimed in claim 9 , wherein the metal electrode of the electric device being through by the via hole is a drain electrode.

Assignees

• Delta Electronics Inc

Inventors

• Tsai Hsin-Chang
• Lee Peng-Hsin

Classifications

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9226

  with via interconnections · CPC title