Apparatus and method of rectifying resolver output signal

Patent metadata

Field	Value
Publication number	US-10419002-B1
Application number	US-201816191729-A
Country	US
Kind code	B1
Filing date	Nov 15, 2018
Priority date	Jul 27, 2018
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

An apparatus for rectifying a resolver output signal may include: a resolver configured to receive an excitation signal and to output a resolver output signal based on the excitation signal, the excitation signal indicating a position of a rotor of a motor; a microprocessor configured to receive a reference rectification signal generated by rectification of the excitation signal and to output a delay signal by delaying the reference rectification signal according to a preset value; and a delay amount detection circuit configured to receive a reference excitation signal generated by rectification of the resolver output signal, to receive the delay signal from the microprocessor, to compare the reference excitation signal with the delay signal, and to output a phase difference detection signal and a delay amount excess/shortage signal to the microprocessor.

First claim

What is claimed is:

1. An apparatus for rectifying a resolver output signal, comprising:
a resolver configured to receive an excitation signal and to output a resolver output signal based on the excitation signal, the excitation signal indicating a position of a rotor of a motor;
a microprocessor configured to receive a reference rectification signal generated by rectification of the excitation signal and to output a delay signal by delaying the reference rectification signal according to a preset value; and
a delay amount detection circuit configured to receive a reference excitation signal generated by rectification of the resolver output signal, to receive the delay signal from the microprocessor, to compare the reference excitation signal with the delay signal, and to output a phase difference detection signal and a delay amount excess/shortage signal to the microprocessor,
wherein the microprocessor includes a switching amplification circuit configured to detect a delay amount of the resolver output signal based on the phase difference detection signal, to output a rectification signal based on the delay amount, to receive the rectification signal, to rectify the resolver output signal by performing a switching operation based on the rectification signal, and to output a compensation signal.

2. The apparatus of claim 1 , wherein:
the delay amount detection circuit includes:
an exclusive-OR gate configured to receive the delay signal and the reference excitation signal and to output the phase difference detection signal which indicates a phase difference between the delay signal and the reference excitation signal; and
a D-type flip-flop configured to receive the reference excitation signal as an input signal, to receive the delay signal as a reference clock, and to output the delay amount excess/shortage signal indicating whether the delay signal leads or lags with respect to the reference excitation signal.

3. The apparatus of claim 1 , wherein:
the microprocessor is configured to detect the delay amount using a output compare function.

4. The apparatus of claim 1 , wherein:
the microprocessor is configured to detect the delay amount using an input capture function.

5. The apparatus of claim 1 , wherein:
the microprocessor includes:
a counter circuit configured to initialize a count when the reference rectification signal is input, such that an interrupt is generated, by increasing the count from an initial value;
a comparison value register configured to store the delay amount;
a comparison circuit configured to detect whether the delay amount is equal to the count; and
an output circuit configured to output a preset output scheduled value when it is detected that the delay amount is equal to the count.

6. The apparatus of claim 1 , wherein:
when a polarity of the rectification signal is equal to a polarity of the resolver output signal, the switching amplification circuit operates as a buffer circuit when the resolver output signal has a positive polarity and operates as an inverting amplifier when the resolver output signal has a negative polarity.

7. The apparatus of claim 1 , wherein:
when a polarity of the rectification signal is opposite of a polarity of the resolver output signal, the switching amplification circuit operates as an inverting amplifier when the resolver output signal has a positive polarity and operates as a buffer circuit when the resolver output signal has a negative polarity.

8. A method for rectifying a resolver output signal output by a resolver, the method, comprising:
outputting, by a microprocessor, a delay signal by delaying an excitation signal output by an excitation signal generator by a preset value;
comparing, by a delay amount detection circuit, the delay signal with a reference excitation signal generated by rectification of the excitation signal;
outputting, by the delay amount detection circuit, a phase difference detection signal and a delay amount excess/shortage signal to the microprocessor;
detecting, by the microprocessor, a delay amount of the resolver output signal based on the phase difference detection signal;
outputting, by the microprocessor, a rectification signal generated by delaying a reference rectification signal by the delay amount;
receiving, by a switching amplification circuit, the rectification signal; and
outputting, by the switching amplification circuit, a compensation signal generated by rectification of the resolver output signal by a switching operation based on the rectification signal.

9. The method of claim 8 , wherein:
the delay amount detection circuit includes an exclusive-OR gate and a D-type flip-flop, and
the outputting of the phase difference detection signal and the delay amount excess/shortage signal comprises:
receiving, by the exclusive-OR gate, the delay signal and the reference excitation signal;
outputting, by the exclusive-OR gate, the phase difference detection signal which indicates a phase difference between the delay signal and the reference excitation signal;
receiving, by the D-type flip-flop, the reference excitation signal as an input signal;
receiving, by the D-type flip-flop, the delay signal as a reference clock; and
outputting, by the D-type flip-flop, the delay amount excess/shortage signal indicating whether the delay signal leads or lags with respect to the reference excitation signal.

10. The method of claim 8 , further comprising:
detecting, by the microprocessor, the delay amount using an output compare function.

11. The method of claim 8 , further comprising:
detecting, by the microprocessor, the delay amount using an input capture function.

12. The method of claim 8 , further comprising:
initializing, by the microprocessor, a count when the reference rectification signal is input, such that an interrupt is generated, by increasing the count from an initial value;
storing, by the microprocessor, the delay amount in a comparison value register;
detecting, by the microprocessor, whether the delay amount is equal to the count; and
outputting, by the microprocessor, output a preset output scheduled value when it is detected that the delay amount is equal to the count.

13. The method of claim 8 , wherein:
when a polarity of the rectification signal is equal to a polarity of the resolver output signal, the switching amplification circuit operates as a buffer circuit when the resolver output signal has a positive polarity and operates as an inverting amplifier when the resolver output signal has a negative polarity.

14. The method of claim 8 , wherein:
when a polarity of the rectification signal is opposite of a polarity of the resolver output signal, the switching amplification circuit operates as an inverting amplifier when the resolver output signal has a positive polarity and operates as a buffer circuit when the resolver output signal has a negative polarity.

Assignees

• Hyundai Motor Co Ltd
• Kia Motors Corp

Inventors

• Lee Myoungseok

Classifications

• H02P6/16 Primary

  Circuit arrangements for detecting position · CPC title

• G01D5/204

  by influencing the mutual induction between two or more coils (G01D5/22 takes precedence) · CPC title

• H03K19/00323 Primary

  Delay compensation · CPC title

• H03K19/17716

  with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register (H03K19/17712 takes precedence) · CPC title

• H02P2209/00

  Indexing scheme relating to controlling arrangements characterised by the waveform of the supplied voltage or current · CPC title