Photodiode array

US10418496B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10418496-B2
Application numberUS-201314647263-A
CountryUS
Kind codeB2
Filing dateNov 26, 2013
Priority dateNov 28, 2012
Publication dateSep 17, 2019
Grant dateSep 17, 2019

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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A photodiode array includes a plurality of photodiodes formed in a semiconductor substrate. Each of the photodiodes includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, provided with respect to the first semiconductor region on one surface side of the semiconductor substrate, and having an impurity concentration higher than an impurity concentration of the first semiconductor region, a third semiconductor region of a second conductivity type, provided with respect to the first semiconductor region on the one surface side so as to surround the second semiconductor region separately from the second semiconductor region, and constituting a light detection region together with the first semiconductor region, and a through-electrode provided within a through-hole passing through the first semiconductor region and the second semiconductor region, and electrically connected to the third semiconductor region.

First claim

Opening claim text (preview).

The invention claimed is: 1. A photodiode array comprising a plurality of photodiodes formed in a semiconductor substrate, wherein the semiconductor substrate comprises a first surface and a second surface, and each of the plurality of photodiodes includes: a first semiconductor region of a first conductivity type disposed in the semiconductor substrate; a second semiconductor region of the first conductivity type disposed in the semiconductor substrate, the second semiconductor region being situated in the first semiconductor region toward the first surface, and having an impurity concentration higher than an impurity concentration of the first semiconductor region; a third semiconductor region of a second conductivity type disposed in the semiconductor substrate, the third semiconductor region being larger than the second semiconductor region when viewed from a thickness direction of the semiconductor substrate, being situated in the first semiconductor region toward the first surface, surrounding the second semiconductor region, constituting a light detection region together with the first semiconductor region, and forming a pn junction with the first semiconductor region; a portion of the first semiconductor region disposed between the second semiconductor region and the third semiconductor region, the portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region being disposed along the first surface of the semiconductor substrate; and a through-electrode disposed within a through-hole passing through the first surface and the second surface of the semiconductor substrate, the first semiconductor region, and the second semiconductor region, the through-electrode extending over the second semiconductor region and of the portion of the first semiconductor region, and the through-electrode being electrically connected to the third semiconductor region, and the second semiconductor region being in direct contact with an insulating layer of the through-hole, being completely spaced apart from the third semiconductor region, and being surrounded by one or more third semiconductor region portions electrically connected to the through-electrode so that the second semiconductor region is surrounded by one monolithic third semiconductor region, or so that the second semiconductor region is surrounded by the one or more third semiconductor region portions that are electrically connected to the same through-electrode. 2. The photodiode array according to claim 1 , wherein a distance between an inner edge and an outer edge of the second semiconductor region is larger than a distance between the outer edge of the second semiconductor region and an inner edge of the third semiconductor region. 3. The photodiode array according to claim 1 , wherein an inner edge of the third semiconductor region surrounds an aperture of the through-hole on the second surface when viewed from the thickness direction of the semiconductor substrate. 4. The photodiode array according to claim 1 , wherein each of the plurality of photodiodes includes a contact electrode formed on the first surface and electrically connecting the third semiconductor region and the through-electrode, and an outer edge of the contact electrode surrounds an aperture of the through-hole on the second surface when viewed from the thickness direction of the semiconductor substrate. 5. The photodiode array according to claim 1 , wherein an aperture of the through-hole on the first surface exhibits a circular shape. 6. The photodiode array according to claim 1 , wherein the third semiconductor region is separated from a peripheral circumference of the second semiconductor region, the second semiconductor region having a depth that is larger than a depth of the third semiconductor region. 7. The photodiode array according to claim 1 , wherein the through-electrode is physically in contact with the third semiconductor region. 8. The photodiode array according to claim 1 , further comprising a fourth semiconductor region, wherein the third semiconductor region is physically separate from the fourth semiconductor region, and the third semiconductor region has a depth that is smaller than the depth of the second semiconductor region and the fourth semiconductor region.

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What does patent US10418496B2 cover?
A photodiode array includes a plurality of photodiodes formed in a semiconductor substrate. Each of the photodiodes includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, provided with respect to the first semiconductor region on one surface side of the semiconductor substrate, and having an impurity concentration higher…
Who is the assignee on this patent?
Hamamatsu Photonics Kk
What technology area does this patent fall under?
Primary CPC classification H01L31/022408. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 17 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).