Silicon carbide semiconductor device and method of manufacturing a silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-10418445-B2
Application number	US-201815988764-A
Country	US
Kind code	B2
Filing date	May 24, 2018
Priority date	Jun 9, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

In a vertical MOSFET having a trench gate structure, a lifetime killer region is provided in a p-type epitaxial layer formed by epitaxial growth. The lifetime killer region includes an electron lifetime killer that causes electrons entering the lifetime killer region to recombine and become extinct. As a result, the lifetime killer region decreases the electrons generated at the pn interface of the p-type epitaxial layer and an n-type drift layer and enables a configuration in which electrons are not delivered to the p-type epitaxial layer.

First claim

What is claimed is:

1. A silicon carbide semiconductor device, comprising:
a silicon carbide substrate;
a first semiconductor layer of a first conductivity type that is provided on a front surface of the silicon carbide substrate;
a second semiconductor layer of a second conductivity type that is provided on a first side of the first semiconductor layer opposite a second side of the first semiconductor layer which faces the silicon carbide substrate;
a first semiconductor region of the second conductivity type that is selectively provided in the second semiconductor layer and that controls electron lifetime;
a second semiconductor region of the first conductivity type that is selectively provided in the second semiconductor layer at a position shallower than a position of the first semiconductor region and that has an impurity concentration that is higher than that of the silicon carbide substrate;
a third semiconductor region of the second conductivity type that is selectively provided in the second semiconductor layer at a position shallower than the position of the first semiconductor region and that has an impurity concentration that is higher than that of the second semiconductor layer;
a trench that penetrates the second semiconductor region and the second semiconductor layer and that reaches the first semiconductor layer;
a gate insulating film that is provided in the trench;
a gate electrode that is provided in the trench on the gate insulating film;
a first electrode that is disposed in contact with the second semiconductor region and the third semiconductor region; and
a second electrode that is provided at a rear surface of the silicon carbide substrate.

2. The silicon carbide semiconductor device according to claim 1 , wherein the first semiconductor region is separated from the trench.

3. The silicon carbide semiconductor device according to claim 1 , wherein the first semiconductor region has crystal defects at a density higher than that of the second semiconductor layer.

4. The silicon carbide semiconductor device according to claim 1 , wherein the first semiconductor region is a region implanted with an element that creates an energy level that is a deep energy level.

5. A method of manufacturing a silicon carbide semiconductor device, comprising:
providing a silicon carbide substrate;
forming a first semiconductor layer of a first conductivity type on a front surface of the silicon carbide substrate;
forming a second semiconductor layer of a second conductivity type on the first semiconductor layer;
selectively forming a first semiconductor region of the second conductivity type in the second semiconductor layer, the first semiconductor region controlling electron lifetime;
selectively forming a second semiconductor region of the first conductivity type in the second semiconductor layer at a position that is shallower than that of the first semiconductor region, the second semiconductor region having an impurity concentration that is higher than that of the silicon carbide substrate;
selectively forming a third semiconductor region of the second conductivity type in the second semiconductor layer at a position shallower than that of the first semiconductor region, the third semiconductor region having an impurity concentration that is higher than that of the second semiconductor layer;
forming a trench that penetrates the second semiconductor region and the second semiconductor layer and reaches the first semiconductor layer;
forming a gate insulating film in the trench;
forming a gate electrode in the trench on the gate insulating film;
forming a first electrode in contact with the second semiconductor region and the third semiconductor region; and
forming a second electrode at a rear surface of the silicon carbide substrate.

6. The method according to claim 5 , wherein selectively forming the first semiconductor region includes forming the first semiconductor region separated from the trench.

7. The method according to claim 5 , wherein selectively forming the first semiconductor region includes forming the first semiconductor region to have a crystal defect density that is higher than that of the second semiconductor layer.

8. The method according to claim 5 , wherein selectively forming the first semiconductor region includes forming the first semiconductor region by implanting an element that creates an energy level that is a deep energy level.

Assignees

• Fuji Electric Co Ltd

Inventors

• Ryo Mina
• Tawara Takeshi
• Miyazato Masaki
• Miyajima Masaaki

Classifications

• H01L29/1608 Primary

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic

• H01L29/66068

  Electricity · mapped topic

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title