Method of forming isolation layer

Patent metadata

Field	Value
Publication number	US-10418271-B2
Application number	US-201414303791-A
Country	US
Kind code	B2
Filing date	Jun 13, 2014
Priority date	Jun 13, 2014
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

First claim

What is claimed is:

1. A method of forming an isolation structure, comprising:
providing a shallow trench isolation in a substrate;
providing a vertical structure over a region of the substrate other than the shallow trench isolation, the vertical structure including a source and a drain disposed over the source;
providing an etch stop layer that includes:
a horizontal upper portion overlying a top of the vertical structure,
a horizontal bottom portion overlying the shallow trench isolation, and
a vertical side portion extending downward from the upper portion and in overlying contact with a side of the source and a side of the drain;

providing an interlayer dielectric (ILD) over the etch stop layer's upper, bottom and side portions;
performing CMP on the ILD, and stopping the CMP upon reaching a top of the etch stop layer's upper portion; and
etching back the ILD and the etch stop layer's side portion, thereby exposing an entirety of the side of the drain,
wherein during the etching back, the ILD and the etch stop layer's side portion are etched together to form the isolation structure.

2. The method of claim 1 , wherein the etch stop layer is made of SiN.

3. The method of claim 1 , wherein the etching back uses wet etching or plasma etching.

4. The method of claim 1 , wherein the etching back uses gas cluster ion beams.

5. The method of claim 1 , wherein the vertical structure includes the source overlying the substrate, a channel overlying the source, and the drain overlying the channel.

6. The method of claim 5 , wherein the vertical structure includes a silicide overlying the drain.

7. The method of claim 6 , wherein:
the silicide has a top surface and a side, and
the etch stop layer is provided such that the vertical side portion is in overlying contact with the side of the silicide.

8. The method of claim 1 , wherein the etching back leaves a top surface of the ILD aligned with a top surface of the source.

9. The method of claim 7 , wherein the etching back removes (i) the etch stop layer's horizontal upper portion and (ii) sections of the etch stop layer's vertical side portions that overlie the channel, the drain and the silicide, and does not remove sections of the etch stop layer's vertical portions that overlie the source.

10. The method of claim 9 , further comprising:
after the etching back the ILD and the etch stop layer's side portion, forming a high-K dielectric layer that includes (i) a horizontal portion that overlies the silicide's top surface, and (ii) a vertical portion that overlies a side of the channel, the side of the drain and the side of the silicide.

11. The method of claim 10 , further comprising:
forming at least one work function metal (WFM) layer that includes (i) a horizontal portion that overlies the high-K dielectric layer's horizontal portion, and (ii) a first vertical portion that overlies the high-K dielectric layer's vertical portion.

12. The method of claim 11 , further comprising:
forming a metal gate layer that includes (i) a horizontal portion that overlies the WFM layer's horizontal portion, and (ii) a first vertical portion that overlies the at least one WFM layer's vertical portion.

13. The method of claim 12 , wherein each of the first layer, the high-K dielectric layer, the at least one WFM layer, and the metal gate layer includes a lower horizontal portion that projects horizontally away from a bottom end of the respective vertical portion.

14. The method of claim 13 , wherein the lower horizontal portion of the high-K dielectric layer overlies the ILD.

15. The method of claim 13 , further comprising:
etching away a distal section of each of the lower horizontal portions, thereby shortening each of the lower horizontal portions.

16. The method of claim 1 , wherein the etching back leaves a remaining section of the etch stop layer's side portion sandwiched between the source and the ILD.

17. A method for manufacturing a vertical gate-all-around device, the method comprising:
providing a shallow trench isolation in a substrate;
providing, over a region of the substrate other than the shallow trench isolation, a source, a channel above the source, a drain above the channel, and a silicide

above the drain; and
forming a gate dielectric layer and a gate electrode around the channel, wherein:
the method further includes, before forming the gate dielectric layer and the gate electrode around the channel:
providing a first layer that includes
a horizontal top portion that overlies a top surface of the silicide,
a horizontal bottom portion that overlies the shallow trench isolation, and
a vertical side portion that in overlying contact with a side surface of each of the source, the channel, the drain and the silicide;

providing an interlayer dielectric that overlies the horizontal top portion, the horizontal bottom portion and the vertical side portion of the first layer; and
performing CMP on the interlayer dielectric, and

the interlayer dielectric includes three layers.

18. The method of claim 17 , further comprising, after performing the CMP:
etching back the interlayer dielectric and the first layer together, thereby exposing a side of the silicide, a side of the drain and a side of the channel; and
forming the gate dielectric layer around the exposed channel and forming the gate electrode over the gate dielectric layer,
wherein the first layer is formed such that the vertical side portion is in direct contact with the side surface of each of the source, the channel, the drain and the silicide.

19. A method for manufacturing a vertical gate-all-around device, the method comprising:
providing a shallow trench isolation in a substrate;
providing a vertical structure over a region of the substrate other than the shallow trench isolation, the vertical structure including a source, a channel above the source and a drain above the channel; and
forming a gate dielectric layer and a gate electrode around the channel, wherein:
the method further includes, before forming the gate dielectric layer and the gate electrode around the channel:
forming a first layer, thereby covering the vertical structure, a part of the first layer overlying the shallow trench isolation;
forming an interlayer dielectric (ILD) layer over the first layer;
performing a chemical mechanical polishing operation on the ILD layer so that a part of the ILD layer remains on a top of the first layer located on a top of the vertical structure; and
etching back the ILD layer and the first layer, thereby exposing a side of the drain and a side of the channel, and

during the etching back, the ILD layer and the etch stop layer's side portion are etched together to form an isolation structure.

20. The method of claim 19 , wherein the first layer is etched such that a part of the first layer remains on a side of the source.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Teng-Chun
• Wang Li-Ting
• Chen De-Fang
• Lin Cheng-Tung
• Peng Chih-Tang
• Wang Chien-Hsun
• Chen Bing-Hung
• Lin Huan-Just
• Lu Yung-Cheng

Classifications

• H10P95/064 Primary

  the removal being chemical etching · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title