Display panel and display device

Patent metadata

Field	Value
Publication number	US-10417954-B2
Application number	US-201715665342-A
Country	US
Kind code	B2
Filing date	Jul 31, 2017
Priority date	Mar 15, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

Provided is a display panel, including a plurality of gate lines extending in a row direction and arranged in a column direction; a plurality of data lines extending in a column direction and arranged in a row direction; a plurality of pixel units arranged in an array of M rows by N columns defined by the plurality of gate lines and the plurality of data lines intersecting each other; a first gate driver connected to pixel units from a first row to a mth row; and a second gate driver connected to pixel units from a (m+1)th row to a Mth row, where pixel units from the first row to the mth row of the nth column are connected to an integrated circuit through one of the plurality of data lines and pixel units from the (m+1)th row to the Mth row of the nth column are connected to the integrated circuit through another one of the plurality of data lines, where M, N, m and n are positive integers satisfying the following conditions: 1<m<M and 1<n<N. Split-screen display is made possible. Different display areas can be driven simultaneously. The display panel can be refreshed at a frequency twice as before without affecting the charging duration of the display panel.

First claim

What is claimed is:

1. A display panel, comprising:
a plurality of gate lines extending in a row direction and sequentially arranged in a column direction, which are numbered sequentially;
a plurality of data lines extending in a column direction and sequentially arranged in a row direction, which are numbered sequentially;
a plurality of pixel units arranged in an array of M rows and N columns defined by the plurality of gate lines and the plurality of data lines intersecting each other, the plurality of pixel units arranged in M rows are numbered from 1 to M sequentially, and the plurality of pixel units arranged in N rows are numbered from 1 to N sequentially, the plurality of pixel units in one column are disposed between two adjacent data lines, wherein a pixel unit group is formed by every two pixel units directly adjacent to each other electrically connected to a same gate line, every two adjacent pixel unit groups are electrically connected to different gate lines, every two pixel unit groups between which one pixel unit group is disposed are electrically connected to a same gate line;
a first gate driver connected to pixel units from a first row to a mth row; and
a second gate driver connected to pixel units from a (m+1)th row to a Mth row, wherein a total number of the plurality of data lines is (N+1), the total number of the plurality of data lines is greater than a column number of the plurality of pixel units, a difference of the total number of the plurality of data lines and the column number of the plurality of pixel units is one, pixel units from the first row to the mth row of the nth column are connected to an integrated circuit through one of the plurality of data lines and pixel units from the (m+1)th row to the Mth row of the nth column are connected to the integrated circuit through another one of the plurality of data lines, wherein each of data lines 2 to N is electrically connected to pixel units in two columns adjacent to the each of the data lines 2 to N, and two pixel units, which are in a same row and electrically connected to a same data line, are connected to different gate lines;
wherein M, N, m and n are positive integers that conform to formulas 1<m<M and 1<n<N.

2. The display panel according to claim 1 , wherein
odd-numbered data lines are electrically connected to pixel units from the first row to the mth row and even-numbered data lines are electrically connected to pixel units from the (m+1)th row to the Mth row; or
even-numbered data lines are electrically connected to pixel units from the first row to the mth row and odd-numbered data lines are electrically connected to pixel units from the (m+1)th row to the Mth row.

3. The display panel according to claim 1 , wherein
a total number of gate lines is 2M, pixel units from the first row to the mth row are connected to the first gate driver through the first to 2mth gate lines, and pixel units from the (m+1)th row to the Mth row are connected to the second gate driver through the (2m+1)th to 2Mth gate lines; and
among pixel units in a same row, at least one of the pixel units is electrically connected to one of the gate lines and other ones of the pixel units are electrically connected to another one of the gate lines.

4. The display panel according to claim 3 , wherein
two of the gate lines are arranged between two adjacent rows of pixel units, and two of the gate lines electrically connected to the same row of pixel units are located along two sides of the same row of pixel units respectively.

5. The display panel according to claim 3 , wherein
among pixel units in a same row, pixel units in the odd-numbered columns and pixel units in the even-numbered columns are electrically connected to different gate lines.

6. The display panel according to claim 1 , wherein
when M is an odd number, the formula m=(M±1)/2 applies; and
when M is an even number, the formula m=M/2 applies.

7. A display device, comprising:
a display panel, comprising:
a plurality of gate lines extending in a row direction and sequentially arranged in a column direction, which are numbered sequentially;
a plurality of data lines extending in a column direction and sequentially arranged in a row direction, which are numbered sequentially;
a plurality of pixel units arranged in an array of M rows and N columns defined by the plurality of gate lines and the plurality of data lines intersecting each other, the plurality of pixel units arranged in M rows are numbered from 1 to M sequentially, and the plurality of pixel units arranged in N rows are numbered from 1 to N sequentially, the plurality of pixel units in one column are disposed between two adjacent data lines, wherein a pixel unit group is formed by every two pixel units directly adjacent to each other electrically connected to a same gate line, every two adjacent pixel unit groups are electrically connected to different gate lines, every two pixel unit groups between which one pixel unit group is disposed are electrically connected to a same gate line;
a first gate driver connected to pixel units from a first row to a mth row; and
a second gate driver connected to pixel units from a (m+1)th row to a Mth row, wherein a total number of the plurality of data lines is (N+1), the total number of the plurality of data lines is greater than a column number of the plurality of pixel units, a difference of the total number of the plurality of data lines and the column number of the plurality of pixel units is one, pixel units from the first row to the mth row of the nth column are connected to an integrated circuit through one of the plurality of data lines and pixel units from the (m+1)th row to the Mth row of the nth column are connected to the integrated circuit through another one of the plurality of data lines, wherein each of data lines 2 to N is electrically connected to pixel units in two columns adjacent to the each of the data lines 2 to N, and two pixel units, which are in a same row and electrically connected to a same data line, are connected to different gate lines;
wherein M, N, m and n are positive integers that conform to formulas 1<m<M and 1<n<N.

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Yang Kangpeng
• Xu Yumin
• Zheng Chao
• Liu Shaofan
• Chen Xiaomeng

Classifications

• G09G2310/0205

  Simultaneous scanning of several lines in flat panels · CPC title

• G09G2310/0221

  with use of split matrices (G09G3/3644 and G09G3/3666 take precedence) · CPC title

• G09G2310/0218

  with collection of electrodes in groups for n-dimensional addressing · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title