Sensors global bus

Patent metadata

Field	Value
Publication number	US-10417172-B2
Application number	US-201715685783-A
Country	US
Kind code	B2
Filing date	Aug 24, 2017
Priority date	Apr 28, 2014
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

Systems, methods and apparatus are described that offer improved performance of a sensor bus. A method includes transmitting a first command on a serial bus while operating in a first mode of operation, exchanging first data with the first device in accordance with a second protocol associated with the second mode of operation, and exchanging second data with the first device in accordance with the second protocol after the first period of time. The first command may be transmitted in accordance with a first protocol to cause a first device to operate in a second mode of operation. The first device may be idle for a first period of time after the first data has been exchanged.

First claim

What is claimed is:

1. A method performed in a data communication interface, comprising:
initiating a transaction on a serial bus in accordance with a first protocol in a first mode of operation, wherein initiating the transaction includes transmitting a start condition and an address that selects a first device, and wherein the address is followed in the transaction by a first command code configured to cause the first device to operate in a second mode of operation;
exchanging first data with the first device in accordance with a second protocol associated with the second mode of operation, wherein the first device is idle for a first period of time after the first data has been exchanged; and
exchanging second data with the first device in accordance with the second protocol after the first period of time.

2. The method of claim 1 , wherein a second device and a third device exchange third data in accordance with a third protocol before the second data is exchanged.

3. The method of claim 2 , wherein the second device is a bus master device that causes the third device to operate in the first mode of operation before the third data is exchanged.

4. The method of claim 2 , further comprising:
determining that the serial bus is idle after the third data is exchanged; and
initiating the exchange of the second data with the first device after the third data has been exchanged and before the first device is returned to the first mode of operation.

5. The method of claim 1 , wherein a fourth device and a fifth device exchange fourth data in accordance with the first protocol before the second data is exchanged.

6. The method of claim 1 , further comprising:
transmitting a second command code on the serial bus after exchanging the first data, wherein the second command code is transmitted in accordance with the first protocol to cause a sixth device to operate in a mode of operation that is different from the second mode of operation; and
exchanging fifth data with the sixth device before exchanging the second data with the first device.

7. The method of claim 1 , wherein the first protocol is compatible with an Inter-Integrated Circuit (I2C) protocol.

8. The method of claim 1 , wherein the second protocol is compatible with an Improved Inter-Integrated Circuit (I3C) protocol.

9. The method of claim 1 , wherein the first data is exchanged in symbols that control signaling state of two wires of the serial bus.

10. The method of claim 1 , wherein a double data rate clock controls transmission of the first data.

11. An apparatus for data communication, comprising:
a transceiver that couples the apparatus to a serial bus; and
a processing circuit configured to:
initiate a transaction on the serial bus in accordance with a first protocol in a first mode of operation, wherein the transaction is initiated by transmitting a start condition and an address that selects a first device, and wherein the address is followed in the transaction by a first command code configured to cause the first device to operate in a second mode of operation;
exchange first data with the first device in accordance with a second protocol associated with the second mode of operation, wherein the first device is idle for a first period of time after the first data has been exchanged; and
exchange second data with the first device in accordance with the second protocol after the first period of time.

12. The apparatus of claim 11 , wherein a second device and a third device exchange third data in accordance with a third protocol before the second data is exchanged.

13. The apparatus of claim 12 , wherein the second device is a bus master that causes the third device to operate in the first mode of operation before the third data is exchanged.

14. The apparatus of claim 12 , wherein the processing circuit is further configured to:
determine when the serial bus is idle after the third data is exchanged; and
initiate the exchange of the second data with the first device when the serial bus is idle and before the first device is returned to the first mode of operation.

15. The apparatus of claim 11 , wherein a fourth device and a fifth device exchange fourth data in accordance with the first protocol before the second data is exchanged.

16. The apparatus of claim 11 , wherein the processing circuit is further configured to:
transmit a second command code on the serial bus after exchanging the first data, wherein the second command code is transmitted in accordance with the first protocol to cause a sixth device to operate in a mode of operation that is different from the second mode of operation; and
exchange fifth data with the sixth device before exchanging the second data with the first device.

17. The apparatus of claim 11 , wherein the first protocol is compatible with an Inter-Integrated Circuit (I2C) protocol.

18. The apparatus of claim 11 , wherein the second protocol is compatible with an Improved Inter-Integrated Circuit (I3C) protocol.

19. The apparatus of claim 11 , wherein the first data is exchanged in symbols that control signaling state of two wires of the serial bus.

20. The apparatus of claim 11 , wherein a double data rate clock controls transmission of the first data.

21. An apparatus comprising:
means for selecting modes of operation of one or more devices coupled to a serial bus, operable to initiate a transaction in accordance with a first protocol in a first mode of operation, wherein the transaction is initiated by transmitting a start condition and an address that selects a first device, and wherein the address is followed in the transaction by a first command code configured to cause the first device to operate in a second mode of operation; and
means for exchanging data over the serial bus, wherein the means for exchanging data is operable to:
exchange first data with the first device in accordance with a second protocol associated with the second mode of operation, wherein the first device is idle for a first period of time after the first data has been exchanged; and
exchange second data with the first device in accordance with the second protocol after the first period of time.

22. The apparatus of claim 21 , wherein a second device and a third device exchange third data in accordance with a third protocol before the second data is exchanged, and
wherein the means for exchanging data is operable to initiate the exchange of the second data with the first device when the serial bus is idle after the third data has been exchanged and before the first device is returned to the first mode of operation.

23. The apparatus of claim 21 , wherein the means for selecting the modes of operation of the one or more devices is operable to transmit a second command code on the serial bus after exchanging the first data, wherein the second command code is transmitted in accordance with the first protocol to cause a fourth device to operate in a mode of operation that is different from the second mode of operation, and
wherein the means for exchanging data is operable to exchange fourth data with the fourth device before exchanging the second data with the first device.

24. The apparatus of claim 21 , wherein the first protocol is compatible with an Inter-Integrated Circuit (I2C) protocol.

25. The apparatus of claim 21 , wherein the second protocol is compatible with an Improved Inter-Integrated Circuit (I3C) protoco

Assignees

• Qualcomm Inc

Inventors

• Pitigoi-Aron Radu
• Wietfeldt Richard Dominic
• Hoffman Douglas Wayne

Classifications

• G06F13/4291

  using a clocked protocol · CPC title

• G06F2213/0016

  Inter-integrated circuit (I2C) · CPC title

• G06F13/4295 Primary

  using an embedded synchronisation · CPC title

• Y02D10/151

  Cross-Sectional Technologies · mapped topic

• Y02D10/14

  Cross-Sectional Technologies · mapped topic