Quantizer including capacitors and operating method of quantizer

Patent metadata

Field	Value
Publication number	US-10411726-B2
Application number	US-201816055193-A
Country	US
Kind code	B2
Filing date	Aug 6, 2018
Priority date	Dec 14, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A quantizer includes: a quantizer capacitor having a first end and a second end; an input calculator that receives input voltages, sums the input voltages, and outputs the summed result to the first end of the quantizer capacitor; a scaler that receives reference voltages and a scale code, generates a scale voltage from the reference voltages depending on the scale code, and outputs the scale voltage to the second end of the quantizer capacitor; and a latch that stores an output voltage of the first end of the quantizer capacitor.

First claim

What is claimed is:

1. A quantizer, comprising:
a quantizer capacitor having a first end and a second end;
an input calculator configured to receive input voltages, to sum the input voltages, and to output a summed result to the first end of the quantizer capacitor;
a scaler configured to receive reference voltages and a scale code, to generate a scale voltage from the reference voltages depending on the scale code, and to output the scale voltage to the second end of the quantizer capacitor; and
a latch configured to store an output voltage of the first end of the quantizer capacitor.

2. The quantizer of claim 1 , wherein the scaler is configured to:
further receive a clock signal and a common voltage;
equalize an internal voltage and a voltage of the second end of the quantizer capacitor to the common voltage in a first phase where the clock signal has a first level; and
generate the scale voltage and output the scale voltage to the second end of the quantizer capacitor, in a second phase where the clock signal has a second level.

3. The quantizer of claim 2 , wherein the scaler includes:
scale capacitors connected with the second end of the quantizer capacitor;
scale switches connected to the scale capacitors, respectively; and
a switch connected to the second end of the quantizer capacitor,
wherein, in the first phase, the scale switches respectively transfer the common voltage to the scale capacitors depending on the scale code, and the switch transfers the common voltage to the second end of the quantizer capacitor depending on the clock signal.

4. The quantizer of claim 3 , wherein the reference voltages include a lower reference voltage and an upper reference voltage, and
wherein, in the second phase, depending on a corresponding portion of the scale code, each of the scale switches transfers one of the lower reference voltage and the upper reference voltage to a corresponding scale capacitor of the scale capacitors.

5. The quantizer of claim 3 , wherein the scaler further includes:
a common capacitor connected between the second end of the quantizer capacitor and a node to which the common voltage is supplied.

6. The quantizer of claim 5 , wherein a capacitance of the common capacitor is determined according to a parasitic capacitance of the scaler.

7. The quantizer of claim 3 , wherein, in the second phase, the switch stops transferring the common voltage to the second end of the quantizer capacitor depending on the clock signal.

8. The quantizer of claim 1 , wherein the input calculator is configured to:
further receive a clock signal and a common voltage;
equalize an internal voltage and a voltage of the first end of the quantizer capacitor to the common voltage in a first phase where the clock signal has a first level; and
output the input voltages to the first end of the quantizer capacitor after respectively applying gains to the input voltages, in a second phase where the clock signal has a second level.

9. The quantizer of claim 8 , wherein the input calculator includes:
addition capacitors connected with the first end of the quantizer capacitor;
addition switches connected to the addition capacitors, respectively; and
a switch connected to the first end of the quantizer capacitor,
wherein, in the first phase, the addition switches respectively transfer the common voltage to the addition capacitors depending on the clock signal, and the switch transfers the common voltage to the first end of the quantizer capacitor depending on the clock signal.

10. The quantizer of claim 9 , wherein the addition switches transfer the input voltages to the addition capacitors depending on the clock signal in the second phase.

11. The quantizer of claim 10 , wherein capacitances of the addition capacitors are determined according to the gains applied to the input voltages.

12. The quantizer of claim 8 , wherein the latch further receives the clock signal,
wherein, in the second phase where the clock signal has the second level, the latch stores a first logical level of a voltage of the first end of the quantizer capacitor and stores a second logical level corresponding to an inverted version of the first logical level.

13. The quantizer of claim 12 , further comprising:
a second latch configured to store the first logical level and the second logical level output from the latch and to output the first logical level as a quantized value.

14. The quantizer of claim 13 , further comprising:
a code generator configured to receive the quantized value from the second latch and to adjust the scale code depending on the quantized value.

15. A quantizer, comprising:
a quantizer capacitor having a first end and a second end;
an input calculator including addition capacitors and configured to receive input voltages, to combine the input voltages by using the addition capacitors, and to transfer a combined result to the first end of the quantizer capacitor;
a scaler including scale capacitors and configured to receive reference voltages, to generate a scale voltage by combining the reference voltages by using the scale capacitors, and to transfer the scale voltage to the second end of the quantizer capacitor; and
a latch configured to store a logical level of an output voltage of the first end of the quantizer capacitor.

16. The quantizer of claim 15 , wherein the input calculator is configured to receive an input voltage of a delta-sigma modulator and output voltages of integrators of the delta-sigma modulator as the input voltages.

17. The quantizer of claim 15 , further comprising:
a code generator configured to generate a scale code for controlling a ratio, by which the scale capacitors combine the reference voltages, depending on the logical level output from the latch, such that quantization is performed based on successive approximation.

18. The quantizer of claim 17 , wherein a number of the scale capacitors is determined according to a number of bits that are quantized based on the successive approximation.

19. An operation method of a quantizer which includes a quantizer capacitor, scale capacitors, and addition capacitors, the method comprising:
initializing a scale code;
equalizing voltages of the scale capacitors and the addition capacitors;
combining input voltages by using the addition capacitors, and applying a result of combining the input voltages to a first end of the quantizer capacitor;
combining reference voltages by using the scale capacitors depending on the scale code, and applying a result of combining the reference voltages to a second end of the quantizer capacitor; and
latching a voltage of the first end of the quantizer capacitor.

20. The method of claim 19 , further comprising:
adjusting the scale code depending on the latched voltage,
wherein the equalizing, combining the input voltages to apply the combined result of the input voltages to the first end, and combining the reference voltages to apply the combined result of the reference voltages to the second end are repeated X times, wherein X is selected based on the adjusted scale code.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yong-Woo
• Shi Dai
• Shin Eun Seok

Classifications

• H03M3/422

  having one quantiser only · CPC title

• H03M1/442 Primary

  using switched capacitors · CPC title

• H03M7/3026

  the quantiser being a multiple bit one · CPC title

• H03M3/428 Primary

  with lower resolution, e.g. single bit, feedback · CPC title

• H03M3/452 Primary

  with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input · CPC title