High-speed and low-power pipelined ADC using dynamic reference voltage and 2-stage sample-and-hold

Patent metadata

Field	Value
Publication number	US-10411722-B2
Application number	US-201816168336-A
Country	US
Kind code	B2
Filing date	Oct 23, 2018
Priority date	Oct 26, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.

First claim

What is claimed is:

1. A pipelined analog-digital converter (ADC) comprising a plurality of stages, wherein each stage comprises:
a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path;
a reference voltage generator configured to receive an output of a D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency; and
a comparator configured to comprise a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate an output of the ADC and input to a reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.

2. The pipelined ADC of claim 1 , wherein the 2-stage S/H doubles the conversion time of each stage.

3. The pipelined ADC of claim 1 , wherein:
a first stage of the 2-stage S/H samples and outputs the input signal, and
a second stage of the 2-stage S/H samples the sampled DC signal of the first stage to remove unnecessary high-frequency transactions, thereby significantly reducing a required frequency bandwidth of a subsequent input signal path.

4. The pipelined ADC of claim 1 , wherein the reference voltage generator changes a level of the reference voltage using a digital-analog converter (DAC) in order to reduce parasitic capacitance of the input signal path requiring a high-speed operation and to increase a frequency bandwidth.

5. The pipelined ADC of claim 1 , wherein the reference voltage generator uses a resistive ladder and generates the reference voltage for a comparator of a current stage through multiplexing using output values up to a previous stage.

6. The pipelined ADC of claim 1 , wherein the reference voltage generator uses reference pre-distortion to offset non-linearity of a voltage attributable to the buffer of the 2-stage S/H and to correct an offset of the comparator attributable to an on-die variation.

7. An operating method of a pipelined analog-digital converter (ADC) comprising a plurality of stages, wherein each of the plurality of stages comprises a 2-stage sample-and-hold (S/H), a comparator and a reference voltage generator, and the operating method comprises steps of:
securing a conversion time corresponding to a clock cycle per stage through the 2-stage S/H applying only a buffer to an input signal path;
receiving an output of a D flip-flop of a previous stage as an input signal and generating a required reference voltage during a half cycle of a sample frequency through the reference voltage generator; and
generating an output of the ADC and input to a reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop of the comparator comprising a linear transconductor (LT), a rail-to-rail latch (R2R) and the D flip-flop.

8. The operating method of claim 7 , wherein the step of securing a conversion time corresponding to a clock cycle per stage through the 2-stage S/H applying only a buffer to an input signal path comprises:
sampling and outputting, by a first stage of the 2-stage S/H, the input signal, and
sampling, by a second stage of the 2-stage S/H, the sampled DC signal of the first stage to remove unnecessary high-frequency transactions, thereby significantly reducing a required frequency bandwidth of a subsequent input signal path.

9. The operating method of claim 7 , wherein the step of receiving an output of a D flip-flop of a previous stage as an input signal and generating a required reference voltage during a half cycle of a sample frequency through the reference voltage generator comprises changing a level of the reference voltage using a digital-analog converter (DAC) in order to reduce parasitic capacitance of the input signal path requiring a high-speed operation and to increase a frequency bandwidth.

10. The operating method of claim 7 , wherein the step of receiving an output of a D flip-flop of a previous stage as an input signal and generating a required reference voltage during a half cycle of a sample frequency through the reference voltage generator comprises:
using a resistive ladder, and
generating the reference voltage for a comparator of a current stage through multiplexing using output values up to a previous stage.

11. The operating method of claim 7 , wherein the step of generating an output of the ADC and input to a reference voltage generator of a next stage for generating a reference voltage comprises using reference pre-distortion to offset non-linearity of a voltage attributable to the buffer of the 2-stage S/H and to correct an offset of the comparator attributable to an on-die variation.

Assignees

• Univ Korea Res & Business Foundation Sejong Campus

Inventors

• Chung Hayun Cecillia

Classifications

• H03M1/1205

  Multiplexed conversion systems · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03M1/124 Primary

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H03M1/1235

  Non-linear conversion not otherwise provided for in subgroups of H03M1/12 · CPC title