Semiconductor device including a recessed insulation region and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10411115-B2
Application number	US-201715613813-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Jun 12, 2016
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and the substrate, and in the opening; performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and forming a gate electrode over the insulation structure and covering a portion of the recess region.

First claim

What is claimed is:

1. A method for forming a semiconductor device, comprising:
forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate;
forming an insulation structure between the mask layer and the substrate, and in the opening;
performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and
forming a gate electrode over the insulation structure and covering a portion of the recess region.

2. The method according to claim 1 , wherein the insulation structure is formed at a bottom of the opening and under portions of the mask layer neighboring the opening, a thickness of the insulation structure gradually decreasing along a direction from a sidewall of the opening to a portion of the mask layer neighboring the sidewall of the opening.

3. The method according to claim 1 , wherein the insulation structure is made of an oxide.

4. The method according to claim 3 , further including:
forming an oxidation layer over the substrate, before forming a mask layer, wherein:
the oxidation layer is formed to expose the surface portion of the substrate; and
the insulation structure is formed through a localized oxidation of silicon on the exposed surface portion of the substrate.

5. The method according to claim 1 , wherein performing a thinning process on the insulation structure includes:
using the mask layer as an etch mask to remove a portion of a total thickness of the insulation structure in the opening and to form the recess region at the top of the insulation structure.

6. The method according to claim 5 , wherein a dry etching process is used to remove the portion of the total thickness of the insulation structure.

7. The method according to claim 1 , wherein a ratio of a depth of the recess region to a thickness of a remaining portion of the insulation structure at the bottom of the opening is smaller than 1.

8. The method according to claim 1 , after forming the recess region and before forming the gate electrode, further comprising forming a first doped region in the substrate to surround the insulation structure, the first doped region being doped with first dopant ions, wherein the semiconductor device is a lateral diffused metal oxide semiconductor transistor.

9. The method according to claim 8 , wherein the first doped region is formed in the substrate through an ion implantation process.

10. The method according to claim 9 , wherein the ion implantation process is performed on portions of the substrate under and neighboring the insulation structure.

11. The method according to claim 8 , further comprising: forming a second doped region in the substrate separated from the first doped region, the second doped region being doped with second dopant ions, wherein the gate electrode is located over the second doped region.

12. The method according to claim 11 , after forming the gate electrode, further comprising:
forming a drain region in the first doped region on a side of the insulation structure facing away from the gate electrode, the drain region being doped with first dopant ions; and
forming a source region in a portion of the second doped region exposed by the gate electrode, the source region being doped with first dopant ions.

13. The method according to claim 1 , further comprising: before forming the mask layer, a first doped region is formed in the substrate to surround the insulation structure, the first doped region being doped with first dopant ions, wherein:
the semiconductor device is a lateral diffused metal oxide semiconductor transistor;
the bottom of the opening exposes the first doped region; and
the insulation structure is formed over the first doped region.

14. A semiconductor device, comprising:
a substrate;
an insulation structure on the substrate, a top of the insulation structure having a recess region; and
a gate electrode, over the insulation structure, covering a portion of the recess region, and exposing a remaining portion of the recess region, wherein the recess region is located at a center and the top of the insulation structure.

15. The semiconductor device according to claim 14 , wherein: a thickness of the insulation structure gradually decreases along a direction pointing from a sidewall of the recess region to a portion of the substrate neighboring the recess region.

16. The semiconductor device according to claim 15 , wherein the insulation structure is formed through a localized oxidation of silicon.

17. The semiconductor device according to claim 14 , wherein a ratio of a depth of the recess region to a thickness of the insulation layer at the bottom of the recess region is smaller than 1.

18. The semiconductor device according to claim 14 , further comprising a first doped region in the substrate and surrounding the insulation structure, the first doped region being doped with first dopant ions.

19. The semiconductor device according to claim 18 , further comprising a second doped region in the substrate separated from the first doped region, the second doped region being doped with second dopant ions, wherein the gate electrode is located over a portion of the second doped region.

20. The semiconductor device according to claim 19 , further comprising:
a drain region in the first doped region on a side of the insulation structure facing away from the gate electrode, the drain region being doped with first dopant ions; and
a source region in a portion of the second doped region exposed by the gate electrode, the source region being doped with first dopant ions.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Jung Dae-Sub
• Fang Lei
• Yang Guang Li
• Chen De Yan

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/242

  of Group IV materials · CPC title