Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10411100-B2
Application number	US-201715645844-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Jun 22, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A semiconductor structure including a substrate, a dielectric layer and a polysilicon layer is provided. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. A fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
a dielectric layer, disposed on the substrate; and
a polysilicon layer, disposed on the dielectric layer,
wherein a fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer,
fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer, and
the fluorine dopant peak concentrations are 8×10 15 ions/cm 2 to 1×10 16 ions/cm 2 , 5×10 15 ions/cm 2 to 7×10 15 ions/cm 2 , and 1×10 15 ions/cm 2 to 4×10 15 ions/cm 2 from the top portion to the bottom portion of the polysilicon layer,
wherein an uppermost part of the top portion of the polysilicon layer is at minimum in the fluorine dopant concentration.

2. The semiconductor structure as claimed in claim 1 , wherein the substrate comprises a silicon substrate.

3. The semiconductor structure as claimed in claim 1 , wherein a material of the dielectric layer comprises silicon oxide.

4. The semiconductor structure as claimed in claim 1 , wherein a material of the polysilicon layer comprises doped polysilicon or undoped polysilicon.

5. The semiconductor structure as claimed in claim 1 , wherein the fluorine dopant peak concentrations comprise:
a first fluorine dopant peak concentration, close to the bottom portion of the polysilicon layer; and
a second fluorine dopant peak concentration, close to the top portion of the polysilicon layer.

6. The semiconductor structure as claimed in claim 5 , wherein the fluorine dopant peak concentrations further comprise:
a third fluorine dopant peak concentration, wherein compared to the second fluorine dopant peak concentration, the third fluorine dopant peak concentration is closer to the top portion of the polysilicon layer.

Assignees

• United Microelectronics Corp

Inventors

• Pan Chen-Wei

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/209

  in silicon to make buried insulating layers · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D64/01306 Primary

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title