Blank suitable for use as a body of a supercapacitor, a supercapacitor, and a method of manufacturing a porous silicon volume

Patent metadata

Field	Value
Publication number	US-10410798-B2
Application number	US-201515518774-A
Country	US
Kind code	B2
Filing date	Oct 14, 2015
Priority date	Oct 17, 2014
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A blank suitable for use as a body of a supercapacitor comprises a first porous semiconductor volume and a second porous semiconductor volume, the second porous semiconductor volume laterally surrounded by the first porous semiconductor volume and separated from it by a trench that is suitable for receiving an electrolyte, whereby the first and second porous semiconductor volume comprise channels opening to the trench. A supercapacitor comprises a body formed by using the blank according to any one of the preceding claims, so that the first porous semiconductor volume acts as one electrode and the second porous semiconductor volume acts as another electrode, with an electrolyte in the trench.

First claim

The invention claimed is:

1. A blank suitable for use as a body of a supercapacitor comprising:
a first porous semiconductor volume and a second porous semiconductor volume, the second porous semiconductor volume being separated from the first porous semiconductor volume by a trench that is suitable for receiving an electrolyte, wherein the first and second porous semiconductor volume comprise channels opening to the trench, the second porous semiconductor volume is laterally surrounded by the first porous semiconductor volume and the trench forms a closed form.

2. The blank according to claim 1 , wherein the first porous semiconductor volume and the second porous semiconductor volume are in the same semiconductor layer and wherein the first and second porous semiconductor volumes extend throughout the height of the layer.

3. The blank according to claim 1 , wherein the side edge of the trench of the first porous semiconductor volume and the side edge of the trench of the second porous semiconductor volume each form at least one electrode.

4. The blank according to claim 3 , wherein at least one, both or all of the electrodes has/have been at least partially coated the respective edges so that they are or comprise coated porous semiconductor.

5. The blank according to claim 4 , wherein the coating has been carried out by using atomic layer deposition or any other method for producing conformal layers.

6. The blank according to claim 4 , wherein the coating is or comprises TiN, NbN or at least one electrically conducting oxide or metal.

7. The blank according to claim 1 , wherein the first porous semiconductor volume and the second porous semiconductor volume are or comprise silicon.

8. The blank according to claim 1 , further comprising an insulating layer limiting to the bottom of the first porous semiconductor volume and of the second porous semiconductor volume, and to the bottom of the trench.

9. The blank according to claim 8 , wherein the insulating layer is or comprises a buried oxide layer and/or consists of semiconductor oxide and/or comprises an electrically insulating layer that in particular may be a silicon nitride layer.

10. The blank according to claim 1 , wherein the blank is in a single or double side polished silicon wafer and the first porous semiconductor volume and the second porous semiconductor volume have been formed in a semiconductive silicon layer, wherein the single or double side polished silicon wafer may be n++ or p++ doped.

11. The blank according to claim 10 , wherein the trench is from below limited by a silicon nitride layer or a BOX layer which acts as a sealing.

12. The blank according to claim 1 , wherein:
a) the blank is in a single or double side polished silicon-on-insulator wafer and the first porous semiconductor volume and the second porous semiconductor volume have been formed in the handle layer, whereby the single or double side polished silicon-on-insulator wafer may be n++ or p++ doped;
or

b) the blank is in a single or double side polished silicon wafer that is a silicon-on-insulator wafer comprising a silicon-on-insulator layer, and located on the side opposite to the silicon-on-insulator layer.

13. A supercapacitor comprising a body formed by using a blank comprising a first porous semiconductor volume and a second porous semiconductor volume, the second porous semiconductor volume being separated from the first porous semiconductor volume by a trench that is suitable for receiving an electrolyte, wherein the first and second porous semiconductor volume comprise channels opening to the trench, the second porous semiconductor volume is laterally surrounded by the first porous semiconductor volume, the trench forms a closed form, and wherein the first porous semiconductor volume acts as one electrode and the second porous semiconductor volume acts as another electrode, with an electrolyte in the trench.

14. The supercapacitor according to claim 13 , further comprising electrical contacting points to the electrodes that have been made through a layer that is immediately below the trench.

15. The supercapacitor according to claim 13 , further comprising a sealing lid for sealing the trench, preferably configured to seal the trench only from the top.

16. The supercapacitor according to claim 13 , wherein the supercapacitor is a separatorless supercapacitor in which there is no intervening separator or separator in the trench but the trench itself acts as a separator.

Assignees

• Teknologian Tutkimuskeskus Vtt Oy

Inventors

• Ahopelto Jouni
• Kestutis Grigoras
• Grönberg Leif
• Prunnila Mika

Classifications

• H10W20/496

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• Y02E60/13

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• H01G9/0032

  formation of the dielectric layer · CPC title

• H01G11/08 Primary

  Structural combinations, e.g. assembly or connection, of hybrid or EDL capacitors with other electric components, at least one hybrid or EDL capacitor being the main component · CPC title

• H01G11/74

  Terminals, e.g. extensions of current collectors · CPC title