Multiprocessor system with independent direct access to bulk solid state memory resources

Patent metadata

Field	Value
Publication number	US-10410693-B2
Application number	US-201615342940-A
Country	US
Kind code	B2
Filing date	Nov 3, 2016
Priority date	Apr 9, 2013
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A system includes a plurality of processors, each being coupled to each of remaining processors via a cluster of processor interconnects. The cluster of processor interconnects form a data distribution network. The system further includes a plurality of roots coupled to the processors, each root corresponding to one of the processors. Each root comprises a memory controller, one or more branches coupled to the memory controller, and a plurality of memory leaves coupled to the branches, each memory leaf having one or more solid state memory devices. Each of the branches is associated with one or more of the memory leaves and provides access to the associated memory leaves. Each of the processors can access any one of the memory leaves via a corresponding branch of any one of the roots over the data distribution network.

First claim

What is claimed is:

1. A data processing system, comprising:
a plurality of processors, each having one or more processor cores, wherein each of the processors is coupled to each of remaining processors via a cluster of processor interconnects, the cluster of processor interconnects forming a data distribution network; and
a plurality of roots coupled to the processors, each root corresponding to one of the processors, wherein each root comprises
a memory controller,
one or more branches coupled to the memory controller, and
a plurality of memory leaves coupled to the branches, each memory leaf having one or more solid state memory devices, wherein each of the branches is associated with one or more of the memory leaves and provides access to the associated memory leaves,

wherein each of the processors can access any one of the memory leaves via a corresponding branch of any one of the roots over the data distribution network, and wherein each of the roots utilizes branch connections to individual memory leaves to distribute a chain of read/write requests so that each individual read/write request is directed to a different memory leaf.

2. The system of claim 1 , further comprising a collection of dynamic random access memory (DRAM) devices coupled to memory controllers of the roots, wherein each memory controller of each root is associated with one or more of the DRAM devices over a memory bus.

3. The system of claim 2 , wherein each of the processors can access any one of the DRAM devices associated with the remaining processors over the cluster of processor interconnects.

4. The system of claim 1 , wherein each memory controller comprises:
one or more memory interfaces coupled to the data distribution network to allow any of the processors to access the memory leaves associated with the corresponding root; and
one or more branch interfaces coupled to one or more branches to allow the memory interfaces to access the memory leaves associated with the corresponding root.

5. The system of claim 4 , wherein each of the memory interfaces is coupled to each of the branch interfaces.

6. The system of claim 4 , wherein each branch interface comprises an internal memory hosting a first software stack executed therein, and wherein the first software stack comprises a routing software and non-blocking parallel solid state interface (NBSI) driver.

7. The system of claim 6 , wherein the routing software is configured to route memory access requests from any of the processors to any of the memory leaves associated with the branch interface.

8. The system of claim 6 , wherein the NBSI driver is configured to provide parallel accesses to the associated memory leaves from multiple processors without blocking each other.

9. The system of claim 6 , wherein each branch interface comprises computational resources to coordinate data searched in individual memory leaves and data processing of retrieved data from the individual memory leaves.

10. The system of claim 1 , wherein each branch comprises a leaf interface controller having a second software stack executed therein for accessing the memory leaves associated with the branch.

11. The system of claim 10 , wherein the leaf interface controller is configured with computational resources to search for data within individual memory leaves and data processing of retrieved data from the individual memory leaves.

12. The system of claim 10 , wherein the second software stack comprises a network driver and a solid state driver executed therein.

13. The system of claim 10 , wherein the second software stack further comprises at least one of a database engine, a data compression engine, or a data encryption engine executed therein.

14. The system of claim 10 , wherein each leaf interface controller is configured with computational resources to search for data within the associated memory leaves and data processing of retrieved data from the associated memory leaves.

15. The system of claim 1 , wherein each processor independently accesses the memory leaves without interfering with an access by another processor.

16. The system of claim 1 , wherein each of the processors accesses memory resources through a hierarchy of roots and branches configured for chained data reads or writes (reads/writes) that exploit parallelism associated with the memory resources.

17. The system of claim 1 , wherein the branches distribute a chain of read/write requests so that each read/write request is directed to a different memory leaf.

18. The system of claim 1 , wherein the processors are configured for directly accessing memory resources by determining that a primary host of a data segment is unavailable and retrieving the data segment from a redundant host.

19. The system of claim 18 , wherein the data segment is reconstructed by one of the processors from data protection codes retrieved from the redundant host.

20. The system of claim 18 , wherein the data segment is reconstructed by a root from data protection codes retrieved from the redundant host.

21. The system of claim 18 , wherein the data segment is reconstructed by a branch from data protection codes retrieved from the redundant host.

Assignees

• Emc Corp
• Emc Ip Holding Co Llc

Inventors

• Carlson Jr Frederic Roy
• Himelstein Mark
• Wilford Bruce
• Arai Dan
• Emberson David R

Classifications

• G06F1/00

  Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 (architectures of general purpose stored program computers G06F15/76) · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F16/2246

  Trees, e.g. B+trees · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F15/167 Primary

  using a common memory, e.g. mailbox · CPC title