Data integrity and loss resistance in high performance and high capacity storage deduplication
US-2016224588-A1 · Aug 4, 2016 · US
US10409717B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10409717-B2 |
| Application number | US-201715853210-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 22, 2017 |
| Priority date | May 11, 2017 |
| Publication date | Sep 10, 2019 |
| Grant date | Sep 10, 2019 |
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A data storage device includes a flash memory, a data processing module and a flash memory controller. Corresponding to the operation of a host, the flash memory controller arranges the flash memory to store data, and it stores a mapping table to record the mapping information between the flash memory and the logical address of the host. When the host transmits a trim command to invalidate a specific portion of the mapping table and the host manages to read the data of the specific portion, the flash memory controller sets up a flag to be open so that the data is transmitted to the host without the implement of the data processing module.
Opening claim text (preview).
What is claimed is: 1. A data storage device, comprising: a flash memory; a data processing module; and a flash memory controller, under operation of a host, arranging the flash memory to store data, and storing a mapping table to record mapping information between logical addresses and physical addresses of the data in the flash memory, wherein: when the host transmits a trim command to invalidate a specific portion of the mapping table first and the host reads data corresponding to the specific portion, the flash memory controller sets up a flag to be open so that the data corresponding to the specific portion is transmitted to the host without process of the data processing module, wherein the data corresponding to the specific portion comprises original data and a data integrity field (DIF) for protecting the original data, wherein the data integrity field comprises a guard field, an application field and a reference tag. 2. The data storage device as claimed in claim 1 , wherein: the flag is the last bit of the guard field. 3. The data storage device as claimed in claim 1 , wherein: the flag is a portion of a field, when the host manages to read the data corresponding to the specific portion, the flash memory controller sets up the flag to be open, and sets up another portion of the field other than the flag to be 0 or 1, to comply with a standard of deterministic trim (DRAT). 4. The data storage device as claimed in claim 1 , wherein: the data processing module comprises a randomizer which is coupled to the flash memory controller to scatter the stored data so that voltage of the data is distributed uniformly. 5. The data storage device as claimed in claim 4 , wherein: the data processing module comprises a corrector which is coupled to the randomizer to correct the stored data. 6. The data storage device as claimed in claim 5 , wherein: the data processing module comprises an encryptor which is coupled to the corrector to encrypt the stored data. 7. The data storage device as claimed in claim 6 , wherein: the data processing module comprises a microprocessor which is coupled to the host to receive a command from the host and provides data transmission between the host and the data storage device. 8. The data storage device as claimed in claim 7 , wherein: the randomizer is further utilized to determine whether a flag of data from the flash memory controller is open or closed, wherein: when the flag of the data from the flash memory is open, the data from the flash memory is not processed by the randomizer, the corrector and the encryptor, and the data from the flash memory is directly transmitted to the microprocessor by the flash memory controller; and when the flag of the data from the flash memory is closed, the data from the flash memory is processed by the randomizer, the corrector and the encryptor. 9. The data storage device as claimed in claim 8 , wherein: the flag of the data from the flash memory is a portion of a field, when the flag of the data from the flash memory is open, after the data from the flash memory is received by the microprocessor, the microprocessor sets up the flag of the data from the flash memory to be closed so that the field is 0 or 1 entirely, and adjusted data is transmitted to the host. 10. A method for operating a data storage device which comprises a flash memory, a data processing module and a flash memory controller, the method comprising: arranging the flash memory to store data under operation of a host; storing a mapping table to record mapping information between logical addresses and physical addresses of the data in the flash memory; and when the host transmits a trim command to invalidate a specific portion of the mapping table and the host reads data corresponding to the specific portion, setting up a flag to be open so that the data corresponding to the specific portion is transmitted to the host without process of the data processing module, wherein the data corresponding to the specific portion comprises original data and a data integrity field (DIF) for protecting the original data, wherein the data integrity field comprises a guard field, an application field and a reference tag. 11. The method for operating the data storage device as claimed in claim 10 , wherein: the flag is the last bit of the guard field. 12. The method for operating the data storage device as claimed in claim 10 , wherein the flag is a portion of a field, and the data storage device further comprising: when the host manages to read the data corresponding to the specific portion, setting up the flag to be open, and setting up another portion of the field other than the flag to be 0 or 1, to comply with standard of deterministic trim (DRAT). 13. The method for operating the data storage device as claimed in claim 10 , further comprising: scattering the stored data so that voltage of the data is distributed uniformly by a randomizer of the data processing module. 14. The method for operating the data storage device as claimed in claim 13 , further comprising: correcting the stored data by a corrector of the data processing module. 15. The method for operating the data storage device as claimed in claim 14 , wherein: encrypting the stored data by an encryptor of the data processing module. 16. The method for operating the data storage device as claimed in claim 15 , wherein: by utilizing a microprocessor of the data processing module, receiving a command from the host and implementing providing data transmission between the host and the data storage device. 17. The method for operating the data storage device as claimed in claim 16 , further comprising: determining whether a flag of data from the flash memory controller is open or closed by the randomizer, wherein: when the flag of the data from the flash memory is open, the data from the flash memory is not processed by the randomizer, the corrector and the encryptor, and the data from the flash memory is directly transmitted to the microprocessor by the flash memory controller; and when the flag of the data from the flash memory is closed, the data from the flash memory is processed by the randomizer, the corrector and the encryptor. 18. The method for operating the data storage device as claimed in claim 17 , wherein: the flag of the data from the flash memory is a portion of a field, when the flag of the data from the flash memory is open, after the data from the flash memory is received by the microprocessor, setting up the flag of the data from the flash memory to be closed so that the field is 0 or 1 entirely by the microprocessor, and transmitting adjusted data to the host.
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by allocating resources to storage systems · CPC title
Logical to physical mapping or translation of blocks or pages · CPC title
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