Apparatus and method for loop flattening and reduction in a single instruction multiple data (SIMD) pipeline

Patent metadata

Field	Value
Publication number	US-10409601-B2
Application number	US-201715859046-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Dec 29, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions. For example, one embodiment of a processor comprises: a decoder to decode a broadcast instruction to generate a decoded broadcast instruction identifying a plurality of operations, the broadcast instruction including an opcode, first and second source operands, and at least one destination operand, the broadcast instruction having a split value associated therewith; a first source register associated with the first source operand to store a first plurality of packed data elements; a second source register associated with the second source operand to store a second plurality of packed data elements; execution circuitry to execute the operations of the decoded broadcast instruction, the execution circuitry to copy a first number of contiguous data elements from the first source register to a first set of contiguous data element locations in a destination register specified by the destination operand, the execution circuitry to further copy a second number of contiguous data elements from the second source register to a second set of contiguous data element locations in the destination register, wherein the execution circuitry is to determine the first number and the second number in accordance with the split value associated with the broadcast instruction.

First claim

What is claimed is:

1. A processor comprising:
a decoder to decode a broadcast instruction to generate a decoded broadcast instruction identifying a plurality of operations, the broadcast instruction including an opcode, first and second source operands, and at least one destination operand, the broadcast instruction having a split value associated therewith;
a first source register associated with the first source operand to store a first plurality of packed data elements;
a second source register associated with the second source operand to store a second plurality of packed data elements;
execution circuitry to execute the operations of the decoded broadcast instruction, the execution circuitry to copy a first one or more contiguous data elements of the first plurality of packed data elements from the first source register to a first set of contiguous data element locations in a destination register specified by the destination operand, the execution circuitry to further copy a second number of one or more contiguous data elements of the second plurality of packed data elements from the second source register to a second set of contiguous data element locations in the destination register,
wherein the execution circuitry is configured to determine the first set of contiguous data element locations and the second set of contiguous data element locations in accordance with the split value associated with the broadcast instruction.

2. The processor of claim 1 wherein the split value is to be included in an immediate of the broadcast instruction.

3. The processor of claim 1 wherein the split value is to be included as an operand of the broadcast instruction and stored in a third source register.

4. The processor of claim 1 wherein the split value comprises an integer value having a range of 0 to N−1, where N comprises a number of data elements in the destination register.

5. The processor of claim 4 wherein the execution circuitry is to further use the split value to identify a location at which to stop reading from the first set of data elements and start reading from the second set of data elements.

6. The processor of claim 1 wherein the broadcast instruction is to identify a mask field, the execution circuitry configured to use the mask field to determine whether to write a mask value to a data element location in the first set of contiguous data element locations or second set of contiguous data element locations of the destination register instead of one of the first or second plurality of packed data elements from the first or second registers, respectively.

7. The processor of claim 6 wherein the mask field is to be included in an immediate of the broadcast instruction or stored in a third source register.

8. The processor of claim 6 wherein the mask value comprises a packed data element comprising all zeroes or a packed mask value stored in a mask source register.

9. A method comprising:
decoding a broadcast instruction to generate a decoded broadcast instruction identifying a plurality of operations, the broadcast instruction including an opcode, first and second source operands, and at least one destination operand, the broadcast instruction having a split value associated therewith;
storing a first plurality of packed data elements in a first source register associated with the first source operand;
storing a second plurality of packed data elements in a second source register associated with the second source operand;
execute the plurality of operations of the decoded broadcast instruction including:
copying a first one or more contiguous data elements of the first plurality of packed data elements from the first source register to a first set of contiguous data element locations in a destination register specified by the destination operand, and
copying a second one or more contiguous data elements of the second plurality of packed data elements from the second source register to a second set of contiguous data element locations in the destination register,
wherein the first set of contiguous data element locations and the second set of contiguous data element locations are determined in accordance with the split value associated with the broadcast instruction.

10. The method of claim 9 wherein the split value is to be included in an immediate of the broadcast instruction.

11. The method of claim 9 wherein the split value is to be included as an operand of the broadcast instruction and stored in a third source register.

12. The method of claim 9 wherein the split value comprises an integer value having a range of 0 to N−1, where N comprises a number of data elements in the destination register.

13. The method of claim 12 wherein the split value is to be used to identify a location at which to stop reading from the first set of data elements and start reading from the second set of data elements.

14. The method of claim 9 wherein the broadcast instruction is to identify a mask field, the mask field to be used to determine whether to write a mask value to a data element location in the first set of contiguous data element locations or second set of contiguous data element locations of the destination register instead of one of the first or second plurality of packed data elements from the first or second registers, respectively.

15. The method of claim 14 wherein the mask field is to be included in an immediate of the broadcast instruction or stored in a third source register.

16. The method of claim 14 wherein the mask value comprises a packed data element comprising all zeroes or a packed mask value stored in a mask source register.

17. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
decoding a broadcast instruction to generate a decoded broadcast instruction identifying a plurality of operations, the broadcast instruction including an opcode, first and second source operands, and at least one destination operand, the broadcast instruction having a split value associated therewith;
storing a first plurality of packed data elements in a first source register associated with the first source operand;
storing a second plurality of packed data elements in a second source register associated with the second source operand;
execute the plurality of operations of the decoded broadcast instruction including:
copying a first one or more contiguous data elements of the first plurality of packed data elements from the first source register to a first set of contiguous data element locations in a destination register specified by the destination operand, and
copying a second one or more contiguous data elements of the second plurality of packed data elements from the second source register to a second set of contiguous data element locations in the destination register,
wherein the first set of contiguous data element locations and the second set of contiguous data element locations are determined in accordance with the split value associated with the broadcast instruction.

18. The non-transitory machine-readable medium of claim 17 wherein the split value is to be included in an immediate of the broadcast instruction.

19. The non-transitory machine-readable medium of claim 17 wherein the split value is to be included as an operand of the broadcast instruction and stored in a third source register.

20. The non-transitory machine-readable medium of claim 17 wherein the split valu

Assignees

• Intel Corp

Inventors

• Brown William M
• Schulz Roland
• Raman Karthik

Classifications

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30018

  Bit or string instructions · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30098

  Register arrangements · CPC title