Controlling power delivery to a processor via a bypass

Patent metadata

Field	Value
Publication number	US-10409346-B2
Application number	US-201816056949-A
Country	US
Kind code	B2
Filing date	Aug 7, 2018
Priority date	May 31, 2013
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A system on chip (SoC) comprising:
a plurality of processor cores formed on a first die, including a first processor core and a second processor core, the first and second processor cores to operate at a corresponding controllable voltage and frequency;
a cache memory shared by two or more of the plurality of processor cores;
an integrated memory controller formed on the first die to couple the plurality of processor cores to a memory;
a first integrated voltage regulator formed on the first die, the first integrated voltage regulator having a first input to receive a first input voltage from a first voltage rail and a first output to provide a first regulated voltage to the first processor core via a first operating voltage rail, the first integrated voltage regulator comprising:
first control circuitry to produce a first plurality of gate control signals; and
a first plurality of p-type MOSFETs (pFETs) coupled to the first control circuitry, each of the first plurality of pFETs to receive a corresponding one of the first plurality of gate control signals, the first plurality of pFETs to generate the first regulated voltage by regulating the first input voltage based on the first plurality of gate control signals received from the first control circuitry;

a second integrated voltage regulator formed on the first die, the second integrated voltage regulator having a second input to receive a second input voltage from a second voltage rail and a second output to provide a second regulated voltage to the second processor core via a second operating voltage rail, the second integrated voltage regulator comprising:
second control circuitry to produce a second plurality of gate control signals; and
a second plurality of pFETs coupled to the second control circuitry, each of the second plurality of pFETs to receive a corresponding one of the second plurality of gate control signals, the second plurality of pFETs to generate the second regulated voltage by regulating the second input voltage based on the second plurality of gate control signals received from the second control circuitry;

a power controller to determine an operating voltage for the plurality of processor cores;
first pass-through circuitry coupled to the first voltage rail and the first operating voltage rail;
second pass-through circuitry coupled to the second voltage rail and the second operating voltage rail;
wherein, in a first mode, the first pass-through circuitry is to selectively couple the first voltage rail to the first operating voltage rail, the second pass-through circuitry is to selectively couple the second voltage rail to the second operating voltage rail, the first and second integrated voltage regulators are to be disabled;
wherein, in a second mode, the first pass-through circuitry is to selectively decouple the first voltage rail from the first operating voltage rail, the second pass-through circuitry is to selectively decouple the second voltage rail from the second operating voltage rail, and the first and second integrated voltage regulators are engaged to provide the first regulated voltage and the second regulated voltage, respectively; and
a Peripheral Component Interconnect Express (PCIe) interface formed on the first die to interface with another circuit.

2. The SoC of claim 1 , wherein operation in the first mode or the second mode is based on a first target operating point for the first processor core and a second target operating point for the second processor core.

3. The SoC of claim 2 , wherein, in the second mode, the first target operating point comprises a first operating voltage and the second target operating point comprises a second operating voltage, and the second operating voltage is different from the first operating voltage.

4. The SoC of claim 2 , wherein, in the first mode, the first target operating point comprises a first operating frequency and the second target operating point comprises a second operating frequency, and the second operating frequency is equal to the first operating frequency.

5. The SoC of claim 1 , wherein the first integrated voltage regulator further comprises an analog-to-digital converter to output a digital code based on comparison of the first regulated voltage to a reference voltage.

6. The SoC of claim 5 , wherein the first integrated voltage regulator further comprises a comparator to compare the first regulated voltage to the reference voltage.

7. The SoC of claim 1 , wherein the SoC further comprises a graphics processor.

8. The SoC of claim 1 , wherein the SoC further comprises an image processor.

9. The SoC of claim 1 , further comprising a bus to communicate regulated voltage levels in the form of voltage identification values.

10. The SoC of claim 1 , wherein the power controller is to control at least the first processor core to operate at a frequency higher than a guaranteed maximum frequency.

11. The SoC of claim 1 , further comprising a shared cache memory coupled to the first processor core and the second processor core.

12. A method comprising:
determining, in a system on chip (SoC) having a first processor core, a second processor core, a first integrated voltage regulator, a second integrated voltage regulator, a power controller and a Peripheral Component Interconnect (PCI) interface, that the first processor core and the second processor core are to operate at least at substantially the same target operating point;
in response to determining that the first processor core and the second processor core are to operate at the at least substantially same target operating point:
disabling the first integrated voltage regulator, the first integrated voltage regulator comprising:
first control circuitry to produce a first plurality of gate control signals; and
a first plurality of p-type MOSFETs (pFETs) coupled to the first control circuitry, each of the first plurality of pFETs to receive a corresponding one of the first plurality of gate control signals, the first plurality of pFETs to generate a first regulated voltage by regulating a first input voltage based on the first plurality of gate control signals received from the first control circuitry;

disabling the second integrated voltage regulator, the second integrated voltage regulator comprising:
second control circuitry to produce a second plurality of gate control signals; and
a second plurality of pFETs coupled to the second control circuitry, each of the second plurality of pFETs to receive a corresponding one of the second plurality of gate control signals, the second plurality of pFETs to generate a second regulated voltage by regulating a second input voltage based on the second plurality of gate control signals received from the second control circuitry;

controlling a first pass-through circuit to selectively provide the first input voltage to the first processor core; and
controlling a second pass-through circuit to selectively provide the first input voltage to the second processor core.

13. The method of claim 12 , further comprising in response to determining that the first processor core and the second processor core are not to operate at the at least substantially same target operating point, engaging the first integrated voltage regulator to provide the first regulated voltage to the first processor core and engaging the second integrated voltage regulator to provide the second regulated voltage to the second processor core.

14. A system on chip (SoC) comprising:
a plurality of processor cores formed on a first die, including a first processor core and a second processor core

Assignees

• Intel Corp

Inventors

• Jahagirdar Sanjeev S
• Damaraju Satish K
• Chen Yun-Han
• Wells Ryan D
• Sodhi Inder M
• Sarurkar Vishram
• Drottar Ken
• Choubal Ashish V
• Islam Rabiul

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• Y02D10/152

  Cross-Sectional Technologies · mapped topic