Method and device for the protection of data integrity through an embedded system having a main processor core and a security hardware module

Patent metadata

Field	Value
Publication number	US-10404717-B2
Application number	US-201615333771-A
Country	US
Kind code	B2
Filing date	Oct 25, 2016
Priority date	Oct 30, 2015
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A method for protecting data integrity through an embedded system having a main processor core and a security hardware module. The method includes the following: the main processor core generates transmit data, the security hardware module calculates a transmit message authentication code from the transmit data, the main processor core links the transmit data and the transmit message authentication code to form a transmit message, and the main processor core transmits the transmit message to a receiver.

First claim

What is claimed is:

1. A method for protecting data integrity, comprising:
generating, by a main processor core in an embedded system, transmit data;
calculating, by a security hardware circuit in the embedded system, a transmit message authentication code from a copy of the transmit data, wherein the security hardware circuit is separate from the main processor core in the embedded system;
linking, by the main processor core in the embedded system, the transmit data and the transmit message authentication code to form a transmit message;
transmitting, by the main processor core in the embedded system, the transmit message to a receiver; and
recognizing, by the receiver, based on the transmit message from the main processor core in the embedded system, if the transmit message authentication code is calculated with errors, or, if the transmit message authentication code is transmitted with errors from the security hardware circuit to the main processor core.

2. The method as recited in claim 1 , further comprising:
receiving, by the main processor core, a receive message having receive data and a first receive message authentication code;
calculating, by the security hardware module, from the receive message, a second receive message authentication code;
carrying out, by the security hardware module, based on the first receive message authentication code and the second receive message authentication code, an information security test; and
carrying out, by the main processor core, based on the first receive message authentication code and the second receive message authentication code, a functional safety test.

3. The method as recited in claim 2 , wherein, in the information security test, the first receive message authentication code is compared with the second receive message authentication code, if the first receive message authentication code differs from the second receive message authentication code, the information security test fails, and if the first receive message authentication code agrees with the second receive message authentication code, the information security test ends successfully.

4. The method as recited in claim 2 , wherein, in the functional safety test, the first receive message authentication code is compared with the second receive message authentication code, if the first receive message authentication code differs from the second receive message authentication code, the functional safety test fails, and if the first receive message authentication code agrees with the second receive message authentication code, the main processor core uses the receive data.

5. The method as recited in claim 2 , wherein the main processor core or the security hardware module recognize if the second receive message authentication code is calculated with errors.

6. The method as recited in claim 2 , wherein the main processor core recognizes if the second receive message authentication code is transmitted with errors from the security hardware module to the main processor core.

7. A non-transitory machine-readable storage medium on which is stored a computer program for protecting data integrity, the computer program, when executed by a processor, causing:
generating, by a main processor core in an embedded system, transmit data;
calculating, by a security hardware circuit in the embedded system, a transmit message authentication code from a copy of the transmit data wherein the security hardware circuit is separate from the main processor core in the embedded system;
linking, by the main processor core in the embedded system, the transmit data and the transmit message authentication code to form a transmit message;
transmitting, by the main processor core in the embedded system, the transmit message to a receiver; and
recognizing, by the receiver, based on the transmit message from the main processor core in the embedded system, if the transmit message authentication code is calculated with errors, or if the transmit message authentication code is transmitted with errors from the security hardware circuit to the main processor core.

8. A device for protecting data integrity, the device comprising an embedded system including a main processor core and a security hardware circuit, wherein the security hardware circuit is separate from the main processor core,
the main processor core is designed to transmit data, the security hardware circuit is designed to calculate a transmit message authentication code from a copy of the transmit data,
the main processor core is designed to link the transmit data and the transmit message authentication code to form a transmit message,
the main processor core is designed to transmit the transmit message to a receiver,
and the receiver is configured recognize, based on the transmit message, if the transmit message authentication code is calculated with errors, or if the transmit message authentication code is transmitted with errors from the security hardware circuit to the main processor core.

9. The method as recited in claim 1 , wherein the security hardware module and the main processor core are part of the same embedded system.

10. The non-transitory machine-readable storage medium as recited in claim 7 , wherein the security hardware module and the main processor core are part of the same embedded system.

11. The device as recited in claim 8 , wherein the security hardware module and the main processor core are part of the same embedded system.

12. The method as recited in claim 1 , wherein the security hardware module is a hardware security module (HSM).

13. The non-transitory machine-readable storage medium as recited in claim 7 , wherein the security hardware module is a hardware security module (HSM).

14. The device as recited in claim 8 , wherein the security hardware module is a hardware security module (HSM).

Assignees

• Bosch Gmbh Robert

Inventors

• Glas Benjamin
• Gebauer Carsten

Classifications

• G06F21/64 Primary

  Protecting data integrity, e.g. using checksums, certificates or signatures · CPC title

• H04L9/34

  Bits, or blocks of bits, of the telegraphic message being interchanged in time {(for speech signals H04K1/06)} · CPC title

• H04L9/3236

  using cryptographic hash functions · CPC title

• H04L9/0838

  Key agreement, i.e. key establishment technique in which a shared key is derived by parties as a function of information contributed by, or associated with, each of these (network architectures or network communication protocols for key exchange in a packet data network H04L63/061) · CPC title

• H04L63/1466

  Active attacks involving interception, injection, modification, spoofing of data unit addresses, e.g. hijacking, packet injection or TCP sequence number attacks · CPC title