Capacitively coupled level shifter

Patent metadata

Field	Value
Publication number	US-10404256-B2
Application number	US-201916260067-A
Country	US
Kind code	B2
Filing date	Jan 28, 2019
Priority date	Nov 15, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A half bridge GaN circuit is disclosed. The circuit includes a low side power switch configured to be selectively conductive according to one or more input signals, a high side power switch configured to be selectively conductive according to the one or more input signals, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a capacitor, and a logic circuit, wherein the capacitor is configured to capacitively couple a signal based on the input signals to the logic circuit, and the logic circuit is configured to control the conductivity of the high sigh power switch based on the capacitively coupled signal.

First claim

What is claimed is:

1. A half bridge GaN circuit, comprising:
a switch node;
a low side power switch configured to selectively conduct current from the switch node according to one or more input signals;
a high side power switch configured to selectively conduct current to the switch node according to the one or more input signals; and
a high side power switch controller, comprising:
a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node,
a voltage generator configured to generate a second power voltage at a VMID node, wherein the second power voltage is between the first power voltage and the switch voltage, and wherein the second power voltage is generated based on the first power voltage,
a first logic circuit, wherein a first negative power terminal of the first logic circuit is connected to the VMID node, and wherein a first positive power terminal of the first logic circuit is connected to the first power node,
a second logic circuit having a second negative power terminal connected to the switch node, and
a capacitor configured to capacitively couple an output signal from the first logic circuit to an input of the second logic circuit,
wherein the second logic circuit is configured to control the conductivity of the high side power switch based on the capacitively coupled signal.

2. The circuit of claim 1 , wherein in the input signals are referenced to a first voltage and the capacitively coupled signal is referenced to a second voltage.

3. The circuit of claim 2 , wherein the first voltage is a ground voltage and the second voltage changes according to the input signals.

4. The circuit of claim 1 , wherein the input threshold of the logic gate changes according to changes in the voltage of the first power node.

5. The circuit of claim 1 , further comprising a low side power switch controller configured to control the conductivity of the low side power switch according to the one or more input signals, and to generate a level shift signal according to the one or more input signals, wherein the level shift signal causes the first logic circuit to generate the output signal of the first logic circuit.

6. The circuit of claim 1 , wherein the high side power switch controller further comprises:
a third logic circuit, wherein a third negative power terminal of the third logic circuit is configured to receive the second power voltage, and wherein a second positive power terminal of the third logic circuit is configured to receive the first power voltage,
a fourth logic circuit having a fourth negative power terminal connected to the switch node, and
a second capacitor configured to capacitively couple an output signal from the third logic circuit to an input of the fourth logic circuit,
wherein the fourth logic circuit is configured to control the conductivity of the high side power switch based on the capacitively coupled signal.

7. The circuit of claim 6 , wherein the second logic circuit is configured to cause the high side power switch to become conductive in response to the capacitively coupled signal, and wherein the fourth logic circuit is configured to cause the high side power switch to become non-conductive in response to the capacitively coupled signal.

8. The circuit of claim 1 , wherein the voltage generator comprises a Zener diode, and wherein the power voltage at the VMID node is less than the voltage of the power node substantially by a breakdown voltage of the Zener diode.

9. The circuit of claim 1 , wherein the high side power switch controller further comprises a latch, wherein the second logic circuit is configured to generate one or more latch input signals based on the capacitively coupled signal, wherein the latch is configured to receive the latch input signals and to generate one or more latch output signals based on the latch input signals, and wherein the latch output signals control the conductivity of the high sigh power switch.

10. The circuit of claim 9 , wherein the high side power switch controller further comprises a power switch driver, wherein the power switch driver is configured to receive the latch output signals, and to control the conductivity of the high sigh power switch based on the latch output signals.

11. An electronic component, comprising:
a package base; and
at least one GaN-based die secured to the package base and including an electronic circuit comprising:
a switch node,
a low side power switch configured to selectively conduct current from the switch node according to one or more input signals,
a high side power switch configured to selectively conduct current to the switch node according to the one or more input signals, and
a high side power switch controller, comprising:
a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node,
a voltage generator configured to generate a second power voltage at a VMID node, wherein the second power voltage is between the first power voltage and the switch voltage, and wherein the second power voltage is generated based on the first power voltage,
a first logic circuit, wherein a first negative power terminal of the first logic circuit is connected to the VMID node, and wherein a first positive power terminal of the first logic circuit is connected to the first power node,
a second logic circuit having a second negative power terminal connected to the switch node, and
a capacitor configured to capacitively couple an output signal from the first logic circuit to an input of the second logic circuit,

wherein the second logic circuit is configured to control the conductivity of the high side power switch based on the capacitively coupled signal.

12. The electronic component of claim 11 , wherein in the input signals are referenced to a first voltage and the capacitively coupled signal is referenced to a second voltage.

13. The electronic component of claim 12 , wherein the first voltage is a ground voltage and the second voltage changes according to the input signals.

14. The electronic component of claim 11 , wherein the input threshold of the logic gate changes according to changes in the voltage of the first power node.

15. The electronic component of claim 11 , further comprising a low side power switch controller configured to control the conductivity of the low side power switch according to the one or more input signals, and to generate a level shift signal according to the one or more input signals, wherein the level shift signal causes the first logic circuit to generate the output signal of the first logic circuit.

16. The electronic component of claim 11 , wherein the high side power switch controller further comprises:
a third logic circuit, wherein a third negative power terminal of the third logic circuit is configured to receive the second power voltage, and wherein a second positive power terminal of the third logic circuit is configured to receive the first power voltage,
a fourth logic circuit having a fourth negative power terminal connected to the switch node, and
a second capacitor configured to capacitively couple an output signal from the third logic circuit to an input of the fourth logic circuit,
wherein the fourth logic circuit is configured to control the conductivity of the high side power switch based on the capacitively coupled signal.

17. The electronic component of claim 16 , wherein the second logic circuit is configured to cause the high side power switch to become

Assignees

• Navitas Semiconductor Inc

Inventors

• Sharma Santosh
• Giandalia Marco
• Kinzer Daniel Marvin
• Ribarich Thomas

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/00

  Package configurations · CPC title