Multi-level inverter with flying capacitor topology

Patent metadata

Field	Value
Publication number	US-10404154-B2
Application number	US-201615054647-A
Country	US
Kind code	B2
Filing date	Feb 26, 2016
Priority date	Mar 26, 2014
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

First claim

We claim:

1. A method comprising:
generating a periodic waveform having a first frequency by switching, at a second frequency and at staggered times, each of a plurality of MOSFET transistors connected in series in a first bank of a multi-level inverter, wherein the second frequency is greater than the first frequency.

2. The method of claim 1 , wherein the switching of each of the plurality of MOSFET transistors includes switching at the staggered times more than two of the plurality of MOSFET transistors, and wherein a voltage rating of each of the plurality of MOSFET transistors is one half or less than a voltage rating of a direct-current voltage at an input to the multi-level inverter.

3. The method of claim 1 , wherein a voltage rating of a direct-current voltage at an input to the multi-level inverter is greater than a voltage rating of each of the plurality of MOSFET transistors and up to a sum of the voltage ratings of the plurality of MOSFET transistors.

4. The method of claim 1 , wherein the switching of each of the plurality of MOSFET transistors occurs at the second frequency of 50kHz to 300kHz, and wherein each of the plurality of MOSFET transistors are rated for 80V to 150V.

5. The method of claim 1 , further comprising
switching, at the staggered times, each of a second plurality of MOSFET transistors connected in a second bank of the multi-level inverter, each of the second plurality of MOSFET transistors being switched at a common time as a respective one of the plurality of MOSFET transistors.

6. The method of claim 5 , further comprising:
adjusting switching duty cycles of one of the second plurality of MOSFET transistors and the respective one of the plurality of MOSFET transistors switched at the common time to different values such that voltage across one of a plurality of switching capacitors in the multi-level inverter is compensated in response to switch mismatches.

7. The method of claim 5 , wherein the switching at the second frequency and at the staggered times produces an effective frequency, at a node connecting the first bank to the second bank, that is a product of a total quantity of the plurality of MOSFET transistors in the first bank multiplied by the second frequency.

8. A multi-level inverter comprising:
a first bank and a second bank of series connected switches, the first bank and the second bank connected in series between an input voltage terminal and a reference voltage terminal;
a plurality of capacitors, each of the plurality of capacitors having a first capacitor terminal connected between two adjacent ones of the switches of the first bank and a second capacitor terminal connected between two adjacent ones of the switches of the second bank; and
a controller configured to cause the multi-level inverter to generate a periodic waveform having a first frequency by controlling a plurality of switch pairs such that each switch pair is switched at staggered times with respect to other ones of the plurality of switch pairs during a periodic switching cycle, wherein the periodic switching cycle has a second frequency greater than the first frequency, and wherein each switch pair comprises one of the switches of the first bank and a respective one of the switches of the second bank.

9. The method of claim 1 , wherein the switching at the staggered times each of the plurality of MOSFET transistors comprises:
turning on and off any one MOSFET transistor of the plurality of MOSFET transistors with a time delay between turning off the one MOSFET transistor the plurality of MOSFET transistors and turning on another MOSFET transistor the plurality of MOSFET transistors.

10. The method of claim 1 , further comprising
switching at the staggered times each of a second plurality of MOSFET transistors connected in a second bank of the multi-level inverter, each of the second plurality of MOSFET transistors being switched at a common time and in an opposite state as a respective one of the plurality of MOSFET transistors.

11. The method of claim 1 , the staggered times being separated by 1/N of the second frequency of the plurality of MOSFET transistors and N being a total quantity of the plurality of MOSFET transistors.

12. The method of claim 1 , further comprising:
changing a switching duty cycle of each of the plurality of the MOSFET transistors such that voltage at an output of the multi-level inverter is varied between two values that are predetermined fractions of a direct-current voltage at an input to the multi-level inverter.

13. The method of claim 1 , further comprising:
switching the plurality of MOSFET transistors in the first bank, a second plurality of MOSFET transistors in a second bank, a third plurality of MOSFET transistors in a third bank, and a fourth plurality of MOSFET transistors in a fourth bank in the multi-level inverter, the first bank being connected in series with the second bank, the third bank being connected in series with the fourth bank, and the first and the second banks being connected to a first phase of an output of the multi-level inverter, and the third and the fourth banks being connected to a second phase of the output of the multi-level inverter.

14. The method of claim 13 , further comprising:
providing a first control signal to switch one of the plurality of MOSFET transistors of the first bank and one of the fourth plurality of MOSFET transistors of the fourth bank; and
providing an inverted first control signal comprising an inverted version of the first control signal to switch one of the second plurality of MOSFET transistors of the second bank and one of the third plurality of MOSFET transistors of the third bank.

15. The method of claim 14 , further comprising,
connecting a different resistor of a plurality of resistors across each of the plurality of MOSFET transistors such that switching capacitors in the multi-level inverter are pre-charge to respective voltages.

16. The multi-level inverter of claim 8 , wherein each switch pair being switched at the staggered times, and the periodic switching cycle having the second frequency, produces an effective frequency, at a node connecting the first bank to the second bank, that is a product of a total quantity of the series connected switches in the first bank multiplied by the second frequency.

17. The multi-level inverter of claim 8 , wherein each of the series connected switches of the first bank and each of the series connected switches of the second bank comprise a MOSFET transistor rated from 80V to 150V.

18. The multi-level inverter of claim 17 , wherein the first bank and the second bank comprise switched resistors bypassing the MOSFET transistors.

19. The multi-level inverter of claim 8 , further comprising
an inductor and a storage capacitor connected in series between a node connecting the first bank to the second bank, and either the input voltage terminal or the reference voltage terminal, wherein the controller is configured to transfer capacitive charge across the storage capacitor to across the input voltage terminal and the reference voltage terminal such that voltage ripple across the input voltage terminal and the reference voltage terminal is reduced.

20. The multi-level inverter of claim 8 , wherein the controller is configured to switch each of the switches of the first bank and of the second bank at the second frequency of 16 kHz or higher.

21. The multi-level inverter of claim 8 , further comprising:
series connected switches in a third

Assignees

• Solaredge Technologies Ltd

Inventors

• Yoscovich Ilan
• Glovinsky Tzachi
• Sella Guy
• Galin Yoav

Classifications

• H02M7/537

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M7/483 Primary

  Converters with outputs that each can have more than two voltages levels · CPC title

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/143

  using compensating arrangements (for reducing noise from the supply in transmission systems H04B15/005) · CPC title

• H02M2001/0054

  Electricity · mapped topic