Logic circuitry using three dimensionally stacked dual-gate thin-film transistors

Patent metadata

Field	Value
Publication number	US-10403759-B2
Application number	US-201815907444-A
Country	US
Kind code	B2
Filing date	Feb 28, 2018
Priority date	Mar 2, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Disclosed is a logic circuit using three-dimensionally stacked dual-gate thin-film transistors, including a substrate, a first dual-gate thin-film transistor on the substrate, a second dual-gate thin-film transistor on the first dual-gate thin-film transistor, and a third dual-gate thin-film transistor on the second dual-gate thin-film transistor, wherein the first dual-gate thin-film transistor, the second dual-gate thin-film transistor and the third dual-gate thin-film transistor are electrically connected to each other. The logic circuit of the invention is configured such that dual-gate thin-film transistors are three-dimensionally stacked, whereby the advantages of the dual-gate structure and of thin-film transistors can be exhibited together and the degree of integration can be drastically increased, and a logic gate is made in the area of a single transistor, thereby remarkably simplifying wire and circuit designs.

First claim

What is claimed is:

1. A logic circuit using three-dimensionally stacked dual-gate thin-film transistors, comprising:
a first dual-gate thin-film transistor on a substrate;
a second dual-gate thin-film transistor on the first dual-gate thin-film transistor; and
a third dual-gate thin-film transistor on the second dual-gate thin-film transistor,
wherein the first dual-gate thin-film transistor, the second dual-gate thin-film transistor and the third dual-gate thin-film transistor are electrically connected to each other,
the first dual-gate thin-film transistor comprises a first bottom-gate electrode, a first dielectric layer on the first bottom-gate electrode, a first source electrode and a first drain electrode on the first dielectric layer, a first semiconductor channel layer between the first source electrode and the first drain electrode, a second dielectric layer on the first source electrode, the first drain electrode and the first semiconductor channel layer, and a first top-gate electrode on the second dielectric layer,
the second dual-gate thin-film transistor comprises a second bottom-gate electrode, a third dielectric layer on the second bottom-gate electrode, a second source electrode and a second drain electrode on the third dielectric layer, a second semiconductor channel layer between the second source electrode and the second drain electrode, a fourth dielectric layer on the second source electrode, the second drain electrode and the second semiconductor channel layer, and a second top-gate electrode on the fourth dielectric layer,
the third dual-gate thin-film transistor comprises a third bottom-gate electrode, a fifth dielectric layer on the third bottom-gate electrode, a third source electrode and a third drain electrode on the fifth dielectric layer, a third semiconductor channel layer between the third source electrode and the third drain electrode, a sixth dielectric layer on the third source electrode, the third drain electrode and the third semiconductor channel layer, and a third top-gate electrode on the sixth dielectric layer,
the first top-gate electrode and the second bottom-gate electrode are the same electrode, and share the same space as each other, and
the second top-gate electrode and the third bottom-gate electrode are the same electrode, and share the same space as each other.

2. The logic circuit of claim 1 , wherein the first bottom-gate electrode, the second bottom-gate electrode, the third bottom-gate electrode, the first source electrode, the second source electrode, the third source electrode, the first drain electrode, the second drain electrode, the third drain electrode, the first top-gate electrode, the second top-gate electrode, and the third top-gate electrode independently include at least one selected from among Au, Al, Ag, Be, Bi, Co, Cu, Cr, Hf, In, Mn, Mo, Mg, Ni, Nb, Pb, Pd, Pt, Rh, Re, Ru, Sb, Ta, Te, Ti, V, W, Zr, Zn, and PEDOT:PSS.

3. The logic circuit of claim 1 , wherein the first bottom-gate electrode is electrically connected to the first top-gate electrode or the second bottom-gate electrode,
the first source electrode is electrically connected to the third source electrode,
the second drain electrode is electrically connected to the third drain electrode, and
the second top-gate electrode or the third bottom-gate electrode is electrically connected to the third top-gate electrode.

4. The logic circuit of claim 3 , wherein electrical connection is realized through a conductive via hole.

5. The logic circuit of claim 1 , wherein the second bottom-gate electrode and the second top-gate electrode of the second dual-gate thin-film transistor are independently controlled.

6. The logic circuit of claim 1 , wherein the first dual-gate thin-film transistor is an N-type transistor, the second dual-gate thin-film transistor is a P-type transistor, and the third dual-gate thin-film transistor is an N-type transistor.

7. The logic circuit of claim 6 , wherein the logic circuit is a NAND gate.

8. The logic circuit of claim 7 , wherein input 1 of the NAND gate is applied to the second top-gate electrode and the third bottom-gate electrode, which share an electrode with each other, and input 2 thereof is applied to the first top-gate electrode and the second bottom-gate electrode, which share an electrode with each other.

9. The logic circuit of claim 1 , wherein the first dual-gate thin-film transistor is a P-type transistor, the second dual-gate thin-film transistor is an N-type transistor, and the third dual-gate thin-film transistor is a P-type transistor.

10. The logic circuit of claim 9 , wherein the logic circuit is a NOR gate.

11. The logic circuit of claim 10 , wherein input 1 of the NOR gate is applied to the second top-gate electrode and the third bottom-gate electrode, which share an electrode with each other, and input 2 thereof is applied to the first top-gate electrode and the second bottom-gate electrode, which share an electrode with each other.

12. The logic circuit of claim 1 , wherein the first semiconductor channel layer includes an n-type organic semiconductor material and/or inorganic semiconductor material, the second semiconductor channel layer includes a p-type organic semiconductor material and/or inorganic semiconductor material, and the third semiconductor channel layer includes an n-type organic semiconductor material and/or inorganic semiconductor material.

13. The logic circuit of claim 12 , wherein the n-type organic semiconductor is at least one selected from among N2200 (poly{[N,N′-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′-bithiophene)}), anthracene, tetracene, hexacene, quinoline, naphthyridine, quinazoline, anthradithiophene, fullerene, perylenedicarboximide, naphthalene diimide, oligo-thiophene, 6,13-bis(triisopropylsilylethynyl)pentacene, 5,11-bis(triethylsilylethynyl)anthradithiophene, 2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene, PCBM, Cu-phthalocyanine, and Zn-phthalocyanine, and
the p-type organic semiconductor is at least one selected from among diF-TES-ADT (2,8-difluoro-5,11-bis(triethylsilylethynyl)anthradithiophene), pentacene, poly(3-hexylthiophene), poly(3-pentylthiophene), poly(3-butylthiophene), poly(benzo[1,2-b:4,5-b′]dithiophene), PBDT2FBT-2EHO (poly(4,8-bis(2-ethylhexyloxy)benzo[1,2-b:4,5-b′]dithiophene-alt-4,7-bis(4-(2-ethylhexyl)-2-thienyl)-5,6-difluoro-2,1,3-benzothiadiazole), and PDPP3T (poly(diketopyrrolopyrrole-terthiophene)).

14. The logic circuit of claim 12 , wherein the n-type inorganic semiconductor includes at least one selected from among ZnO (zinc oxide), ZTO (zinc tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), and IGZO (indium gallium zinc oxide), and
the p-type inorganic semiconductor includes at least one selected from among Ni oxide, Nb oxide, Cu oxide, α-doped Cu oxide (where α is boron, aluminum, gallium or indium), SrCu oxide, β-doped LaCu oxide (where β is sulfur or selenium), and PbS oxide.

15. The logic circuit of claim 1 , wherein the first semiconductor channel layer includes a p-type organic semiconductor material and/or inorganic semiconductor material, the second semiconductor channel layer includes an n-type organic semiconductor material and/or inorganic semiconductor material, and the third semiconductor channel layer includes a p-type organic semiconductor material and/or inorganic semiconductor material.

16. The logic circuit of claim 15 , wherein the n-type organic semiconductor is at least one selected from among N2200 (poly{[N,N′-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(d

Assignees

• Postech Acad Ind Found

Inventors

• Jung Sungjune
• Kwon Jimin

Classifications

• H03K19/0948

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/215

  using field-effect transistors · CPC title

• H01L27/124

  Electricity · mapped topic

• H01L29/78648 Primary

  Electricity · mapped topic