Method of forming semiconductor device including P-N diode

Patent metadata

Field	Value
Publication number	US-10403735-B2
Application number	US-201715409877-A
Country	US
Kind code	B2
Filing date	Jan 19, 2017
Priority date	Jul 14, 2016
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first conductive line on a substrate;
forming a memory cell including a switching device and a data storage element on the first conductive line; and
forming a second conductive line on the memory cell,
wherein forming the switching device includes:
forming a first semiconductor layer;
forming a first doped region using a first doping process of injecting a n-type impurity into the first semiconductor layer;
forming a second semiconductor layer to be thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region;
forming a second doped region using a second doping process of injecting a p-type impurity into an upper region of the second semiconductor layer; and
forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region such that a P-N junction of the P-N diode is formed in the second semiconductor layer.

2. The method as claimed in claim 1 , further comprising:
before the first doping process is performed, forming the first semiconductor layer using a first undoped polysilicon material, and
before the second doping process is performed, forming the second semiconductor layer using a second undoped polysilicon material.

3. The method as claimed in claim 1 , wherein the first doped region is formed in an upper region of the first semiconductor layer.

4. The method as claimed in claim 1 , wherein after the heat treatment process is performed, the first semiconductor layer has an n-type conductivity, and the second semiconductor layer includes a first region having n-type conductivity and a second region having p-type conductivity, the first region of the second semiconductor layer being in contact with the first semiconductor layer.

5. The method as claimed in claim 1 , wherein the P-N junction is formed to be disposed more adjacently to a lower surface of the second semiconductor layer than to an upper surface of the second semiconductor layer.

6. The method as claimed in claim 1 , wherein the P-N junction is formed to be disposed more adjacently to a lower surface of the first semiconductor layer than to the upper surface of the second semiconductor layer.

7. The method as claimed in claim 1 , wherein the P-N junction is formed to be disposed more adjacently to a maximum peak region of a concentration of the n-type impurity in the first semiconductor layer than to a maximum peak region of a concentration of the p-type impurity in the second semiconductor layer.

8. The method as claimed in claim 1 , wherein the P-N diode is formed such that a concentration of the n-type impurity in the first semiconductor layer has a first peak and a second peak lower than the first peak, the first peak being a maximum peak in the first semiconductor layer.

9. The method as claimed in claim 8 , wherein the second peak is formed to be disposed more adjacently to the lower surface of the first semiconductor layer than the first peak.

10. The method as claimed in claim 7 , wherein after the heat treatment process is performed, the first semiconductor layer is formed to have n-type conductivity, the second semiconductor layer is formed to have the first region having n-type conductivity and the second region having p-type conductivity, and an interface between the first region and the second region is formed to be provided as the P-N junction.

11. A method of forming a semiconductor device, the method comprising:
forming a first semiconductor layer on a lower conductive layer, the first semiconductor layer being formed of a first undoped silicon layer;
forming a first doped region including an n-type impurity in the first semiconductor layer using a first doping process;
forming a second semiconductor layer to be thicker than the first semiconductor layer, on the first semiconductor layer including the first doped region, the second semiconductor layer being formed of a second undoped silicon layer;
forming a second doped region including a p-type impurity in an upper region of the second semiconductor layer using a second doping process; and
forming a P-N diode in which a P-N junction is formed in the second semiconductor layer by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region.

12. The method as claimed in claim 11 , wherein the first semiconductor layer is formed to have a thickness in a range of 10Å to 50Å.

13. The method as claimed in claim 11 , wherein the second semiconductor layer is formed to have the thickness 5 to 15 times greater than the thickness of the first semiconductor layer.

14. The method as claimed in claim 11 , wherein after the heat treatment process is performed, an entirety of the first semiconductor layer is formed to have n-type conductivity; the second semiconductor layer is formed to include a first region having n-type conductivity, formed in such a manner that the n-type impurity in the first doped region is diffused and a second region having p-type conductivity, formed in such a manner that the p-type impurity in the second doped region is diffused; and an interface between the first region and the second region is formed to be disposed more adjacently to a lower surface of the second semiconductor layer than to an upper surface of the second semiconductor layer.

15. The method as claimed in claim 11 , wherein after the heat treatment process is performed, a maximum peak of a concentration of the n-type impurity in the first semiconductor layer is formed to be disposed adjacently to the lower conductive layer, and a maximum peak of a concentration of the p-type impurity in the second semiconductor layer is formed to be disposed adjacently to the upper surface of the second semiconductor layer.

16. A method of forming a semiconductor device, the method comprising:
forming a first layer of undoped silicon on a first conductive layer;
forming a first doped region including an n-type impurity in the first layer to form a first semiconductor layer;
forming a second layer of undoped silicon on the first semiconductor layer including the first doped region;
forming a second doped region including a p-type impurity in an upper region of the second layer to form a second semiconductor layer;
performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a first P-N diode including a first P-N junction in the second semiconductor layer;
forming a first electrode layer on the first P-N diode;
forming a first data storage element on the first electrode layer;
forming a second electrode layer on the first data storage element; and
forming an second conductive layer on the second electrode layer.

17. The method as claimed in claim 16 , wherein the first semiconductor layer is formed to have a thickness in a range of 10 Å to 50 Å.

18. The method as claimed in claim 17 , wherein the second semiconductor layer is formed to have the thickness 5 to 15 times greater than the thickness of the first semiconductor layer.

19. The method as claimed in claim 16 , further comprising, before forming the second conductive layer:
performing a first patterning process on the first conductive layer, the first P-N diode, the first electrode layer, the first data storage element and the second electrode

Assignees

• Samsung Electronics Co Ltd

Inventors

• An Ho Kyun
• Im Dong Hyun

Classifications

• H01L45/1675

  Electricity · mapped topic

• H01L29/66136 Primary

  Electricity · mapped topic

• H01L29/861

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L27/224

  Electricity · mapped topic