Switch device and storage unit

Patent metadata

Field	Value
Publication number	US-10403680-B2
Application number	US-201615559571-A
Country	US
Kind code	B2
Filing date	Mar 16, 2016
Priority date	Mar 31, 2015
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A switch device according to an embodiment of the technology includes a first electrode, a second electrode that is disposed to face the first electrode, and a switch layer that is provided between the first electrode and the second electrode. The switch layer contains a chalcogen element. The switch layer includes a first region and a second region which have different composition ratios of one or more of chalcogen elements or different types of the one or more of chalcogen elements. The first region is provided close to the first electrode. The second region is provided closer to the second electrode than the first region.

First claim

What is claimed is:

1. A switch device comprising:
a first electrode;
a second electrode that is disposed to face the first electrode; and
a switch layer that is provided between the first electrode and the second electrode, and contains one or more of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), the switch layer including a first region and a second region which have different composition ratios of the one or more of chalcogen elements or different types of the one or more of chalcogen elements, the first region being provided close to the first electrode, the second region being provided closer to the second electrode than the first region, wherein the switch device is a cross point in a cross point array structure.

2. The switch device according to claim 1 , wherein
the switch layer further contains one or more of incidental elements selected from boron (B), carbon (C), and silicon (Si), and
the switch layer includes the first region and the second region which have different composition ratios of the one or more of incidental elements or different types of the one or more of incidental elements.

3. The switch device according to claim 1 , wherein
the switch layer is changed into a low-resistance state by an increase in an absolute value of a first voltage to a first threshold voltage or higher, and is changed into a high-resistance state by a decrease in the absolute value of the first voltage to a voltage lower than the first threshold voltage when the first voltage is applied between the first electrode and the second electrode, the first voltage causing a voltage of the first electrode to be higher than a voltage of the second electrode,
the switch layer is changed into the low-resistance state by an increase in an absolute value of a second voltage to a second threshold voltage or higher, and is changed into the high-resistance state by a decrease in the absolute value of the second voltage to a voltage lower than the second threshold voltage when the second voltage is applied between the first electrode and the second electrode, the second voltage causing the voltage of the second electrode to be higher than the voltage of the first electrode, and
the switch layer includes the first region and the second region which have different composition ratios of the one or more of chalcogen elements or different types of the one or more of chalcogen elements to allow an absolute value of the first threshold voltage to be different from an absolute value of the second threshold voltage.

4. The switch device according to claim 1 , wherein the switch layer includes a diffusion suppressing layer that suppresses diffusion of the chalcogen elements between the first region and the second region, the chalcogen elements being contained in the first region and the second region.

5. The switch device according to claim 4 , wherein the diffusion suppressing layer contains tungsten (W), molybdenum (Mo), chromium (Cr), vanadium (V), niobium (Nb), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), or a nitride of one or more of elements selected therefrom.

6. The switch device according to claim 1 , wherein the switch layer includes a diffusion suppressing layer that suppresses diffusion of the chalcogen elements between the first region and the second region.

7. A storage unit provided with a plurality of memory cells, each of the memory cells including a memory device and a switch device directly coupled to the memory device, the switch device comprising:
a first electrode;
a second electrode that is disposed to face the first electrode; and
a switch layer that is provided between the first electrode and the second electrode, and contains one or more of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S), the switch layer including a first region and a second region which have different composition ratios of the one or more of chalcogen elements or different types of the one or more of chalcogen elements, the first region being provided close to the first electrode, the second region being provided closer to the second electrode than the first region, wherein the switch device is a cross point in a cross point array structure.

8. The storage unit according to claim 7 , wherein
the switch layer is changed into a low-resistance state by an increase in an absolute value of a third voltage between the first electrode and the second electrode, to a third threshold voltage or higher, and is changed into a high-resistance state by a decrease in the absolute value of the third voltage to a voltage lower than the third threshold voltage when a writing voltage is applied to a corresponding one of the memory cells, the writing voltage decreasing a resistance of the corresponding one of the memory cells,
the switch layer is changed into the low-resistance state by an increase in an absolute value of a fourth voltage between the first electrode and the second electrode, to a fourth threshold voltage or higher, and is changed into the high-resistance state by a decrease in the absolute value of the fourth voltage to a voltage lower than the fourth threshold voltage when an erasing voltage is applied to the corresponding one of the memory cells, the erasing voltage increasing the resistance of the corresponding one of the memory cells, and
the switch layer includes the first region and the second region which have different composition ratios of the one or more of chalcogen elements or different types of the one or more of chalcogen elements to allow an absolute value of the third threshold voltage to be different from an absolute value of the fourth threshold voltage.

9. The storage unit according to claim 8 , wherein the switch layer includes the first region and the second region which have different composition ratios of the one or more of chalcogen elements or different types of the one or more of chalcogen elements to allow the absolute value of the fourth threshold voltage to be larger than the absolute value of the third threshold voltage.

10. The storage unit according to claim 7 , wherein the memory device comprises a bidirectional resistive random access memory.

11. The storage unit according to claim 10 , wherein the memory device includes
a chalcogenide layer serving as an ion source layer that supplies ions, the chalcogenide layer containing one or more of elements selected from copper (Cu), tellurium (Te), zirconium (Zr), and aluminum (Al), and
an oxide layer serving as a resistance-change layer, the oxide layer containing aluminum (Al).

12. The storage unit according to claim 10 , wherein
a resistance-change layer is provided at a position closer to the switch device than an ion source layer, and
a region having a relatively small composition ratio of the one or more of chalcogen elements of the first region and the second region is disposed at a position distant from the memory device.

13. The storage unit according to claim 10 , wherein
a resistance-change layer is provided at a position more distant from the switch device than an ion source layer, and
a region having a relatively small composition ratio of the one or more of chalcogen elements of the first region and the second region is disposed at a position close to the memory device.

14. The storage unit according to claim 7 , further comprising:
a plurality of first wiring lines extending in a predetermined direction; and
a plurality of second wiring lines extending in a direction intersecting the first wiring lines, wherein
each of the memory cells is provided at a position where each of the first

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Ohba Kazuhiro
• Sei Hiroaki
• Nonoguchi seiji
• Sone Takeyuki
• Ikarashi Minoru

Classifications

• H01L27/105

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/142

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic