Methods and apparatus for improving micro-LED devices

US10403678B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10403678-B2
Application numberUS-201715724847-A
CountryUS
Kind codeB2
Filing dateOct 4, 2017
Priority dateMay 7, 2014
Publication dateSep 3, 2019
Grant dateSep 3, 2019

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Abstract

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A μLED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.

First claim

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What is claimed is: 1. A method for fabricating a light emitting diode (LED) device comprising: forming a substrate including a light emitting surface, a portion of the substrate protruding in a direction away from the light emitting surface; forming an epitaxial layer over the portion of the substrate that protrudes in the direction away from the light emitting surface; and forming an active layer on the epitaxial layer, the active layer generating light that is emitted through the light emitting surface of the substrate responsive to an application of an electrical current to the active layer, wherein the protruded portion of the substrate, the formed epitaxial layer, and the formed active layer form a truncated parabolic mesa; wherein at least one of the substrate and the epitaxial layer is formed to comprise a crystal lattice structure with one or more 1122 planes of the crystal lattice structure at an angle from a normal to the light emitting surface that is less than an angle of total internal reflection for the LED device; and wherein the angle of the total internal reflection is determined by a material of the substrate and the crystal lattice structure. 2. The method of claim 1 , further comprising: forming a c-plane of the crystal lattice structure to be non-parallel to the light emitting surface of the substrate. 3. The method of claim 1 , wherein forming the substrate comprises: forming the substrate to include another surface at an opposite side of the light emitting surface, and wherein the portion of the substrate is formed to protrude from a portion of the other surface of the substrate. 4. The method of claim 1 , wherein the crystal lattice structure is formed to comprise a wurzite crystal lattice structure. 5. The method of claim 1 , wherein forming the substrate and forming the epitaxial layer comprises forming the substrate and forming the first epitaxial layer using a semiconductor material. 6. The method of claim 5 , wherein the semiconductor material used to form the substrate and the epitaxial layer comprises Gallium Nitride. 7. The method of claim 1 , wherein the angle of the one or more 1122 planes of the crystal lattice structure is formed to be in a range from 0 degrees to 30 degrees from the normal to the light emitting surface of the substrate. 8. The method of claim 2 , wherein forming the c-plane comprises: forming the c-plane at an angle that is less than the angle of total internal reflection of the LED device. 9. The method of claim 2 , wherein forming the c-plane comprises: forming the c-plane of the crystal lattice structure to be non-parallel to the light emitting surface by an angle in a range from 85 degrees to 105 degrees. 10. The method of claim 1 , further comprising: forming a another epitaxial layer over the active layer, the other epitaxial layer oppositely doped from the epitaxial layer. 11. The method of claim 1 , further comprising: polishing the light emitting surface of the substrate. 12. A method for fabricating an array of a plurality of light emitting diode (LED) devices, the method comprising: forming, for each of the plurality of LED devices, a substrate including a light emitting surface, a portion of the substrate protruding in a direction away from the light emitting surface; forming, for each of the plurality of LED devices, an epitaxial layer over the portion of the substrate that protrudes in the direction away from the light emitting surface; and forming, for each of the plurality of LED devices, an active layer over the epitaxial layer, the active layer generating light that is emitted through the light emitting surface of the substrate responsive to an application of an electrical current to the active layer, wherein the protruded portion of the substrate, the formed epitaxial layer, and the formed active layer of the at least one of the plurality of LED devices form a truncated parabolic mesa; wherein at least one of the substrate and the epitaxial layer of the plurality of LED devices is formed to comprise a crystal lattice structure with one or more 1122 planes of the crystal lattice structure at an angle from a normal to the light emitting surface that is less than an angle of total internal reflection of the plurality of LED devices; and wherein the angle of the total internal reflection for each of the plurality of LED devices is determined by a material of the substrate and the crystal lattice structure of the LED device. 13. The method of claim 12 , further comprising: forming, for each of the plurality of LED devices, a c-plane of the crystal lattice structure to be non-parallel to the light emitting surface of the substrate. 14. The method of claim 12 , wherein forming the substrate comprises: forming the substrate to include another surface at an opposite side of the light emitting surface, and wherein the portion of the substrate is formed to protrude from a portion of the other surface of the substrate. 15. The method of claim 12 , wherein the crystal lattice structure is formed to comprise a wurzite crystal lattice structure. 16. The method of claim 12 , wherein forming the substrate and forming the epitaxial layer comprises forming the substrate and forming the epitaxial layer using a semiconductor material. 17. The method of claim 16 , wherein the semiconductor material used to form the substrate and the first epitaxial layer comprises Gallium Nitride. 18. The method of claim 12 , wherein the angle of the one or more 1122 planes of the crystal lattice structure is formed to be in a range from 0 degrees to 30 degrees from the normal to the light emitting surface of the substrate. 19. A light emitting diode (LED) device created by a process comprising: forming a substrate including a light emitting surface, a portion of the substrate protruding in a direction away from the light emitting surface; forming an epitaxial layer over the portion of the substrate that protrudes in the direction away from the light emitting surface; and forming an active layer on the epitaxial layer, the active layer generating light that is emitted through the light emitting surface of the substrate responsive to an application of an electrical current to the active layer, wherein the protruded portion of the substrate, the formed epitaxial layer, and the formed active layer form a truncated parabolic mesa; wherein at least one of the substrate and the epitaxial layer is formed to comprise a crystal lattice structure with one or more 1122 planes of the crystal lattice structure at an angle from a normal to the light emitting surface that is less than an angle of total internal reflection for the LED device; and wherein the angle of the total internal reflection is determined by a material of the substrate and the crystal lattice structure.

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What does patent US10403678B2 cover?
A μLED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, …
Who is the assignee on this patent?
Facebook Tech Llc
What technology area does this patent fall under?
Primary CPC classification H01L27/156. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 03 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).