Semiconductor package and related methods

Patent metadata

Field	Value
Publication number	US-10403601-B2
Application number	US-201715623580-A
Country	US
Kind code	B2
Filing date	Jun 15, 2017
Priority date	Jun 17, 2016
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first substrate comprising a first dielectric layer coupled between a first metal layer and a second metal layer;
a second substrate comprising a second dielectric layer coupled between a third metal layer and a fourth metal layer;
a first die coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate; and
a second die coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate;
wherein a width of the first substrate is wider than a corresponding width of the second substrate and is configured to facilitate application of a mold compound to the first die and to the second die; and
wherein a length perpendicular to the width of the first substrate is shorter than a corresponding length perpendicular to the width of the second substrate.

2. The semiconductor package of claim 1 , further comprising:
wherein the first dielectric layer comprises an extension extending beyond a length of the first metal layer and a length of the second metal layer, where the length of the first metal layer and the length of the second metal layer are the same; and
wherein the second dielectric layer comprises an extension extending beyond a length of the third metal layer and a length of the fourth metal layer, where the length of the third metal layer and the length of the fourth metal layer are the same.

3. The semiconductor package of claim 1 , wherein:
the first dielectric layer comprises an extension extending beyond a length of the first metal layer and a length of the second metal layer, wherein the length of the first metal layer and the length of the second metal layer are the same, and wherein the length of the third metal layer and the length of the fourth metal layer are the same;
the extension portion of the first dielectric layer extends beyond a length of the third metal layer and a length of the fourth metal layer;
an extension portion of the second dielectric layer extends beyond the length of the extension of the first dielectric layer; and
the lengths of the third and the fourth metal layers extend beyond the lengths of the first and the second metal layers.

4. The semiconductor die of claim 1 , wherein a first side of the first die is coupled with one of the second metal layer and the third metal layer, a second side of the die is coupled with a first side of the first electrical spacer, a second side of the first electrical spacer is coupled with one of the second metal layer and the third metal layer; and
wherein a first side of the second die is coupled with one of the second metal layer and the third metal layer, the second side of the die is coupled with a first side of the first electrical spacer, and a second side of the first electrical spacer is coupled with one of the second metal layer and the third metal layer.

5. The semiconductor package of claim 4 , wherein the first electrical spacer is coupled with the second metal layer, the first die is coupled with the third metal layer, the second electrical spacer is coupled with the third metal layer, and the second die is coupled with the second metal layer.

6. The semiconductor package of claim 4 , wherein both the first electrical spacer and the second electrical spacer are coupled with the third metal layer and both the first die and the second die are coupled with the second metal layer.

7. The semiconductor package of claim 1 , wherein the substrates are biased relative to a molding apparatus by one of two or more springs.

8. The semiconductor package of claim 1 , wherein the first die and the second die comprise one of a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a superjunction field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET) device, a silicon carbide (SiC) device, a SiC BJT, a diode, a Schottky diode, and combination thereof.

9. The semiconductor package of claim 1 , wherein the first electrical spacers is coupled with the first die through solder and the second electrical spacer is coupled with the second die through solder.

10. A power module comprising:
a first substrate comprising a first dielectric layer coupled between a first metal layer and a second metal layer, the first dielectric layer comprising an extension portion extending beyond a length of the first metal layer and a length of the second metal layer and where the length of the first metal layer and the length of the second metal layer are the same;
a second substrate comprising a second dielectric layer coupled between a third metal layer and a fourth metal layer, the second dielectric layer comprising an extension portion extending beyond a length of the third metal layer and a length of the fourth metal layer and where the length of the third metal layer and the length of the fourth metal layer are the same;
a first die coupled with a first electrical spacer coupled in a space between and coupled to the first substrate and the second substrate, a first side of the first die coupled with one of the second metal layer and the third metal layer, a second side of the die coupled with a first side of the first electrical spacer, a second side of the first electrical spacer coupled with one of the second metal layer and the third metal layer; and
a second die coupled with a second electrical spacer coupled in a space between and coupled to the first substrate and the second substrate, a first side of the second die coupled with one of the second metal layer and the third metal layer, the second side of the die coupled with a first side of the first electrical spacer, a second side of the first electrical spacer coupled with one of the second metal layer and the third metal layer;
wherein a width of the first substrate perpendicular to the length of the extension portion of the first dielectric layer is wider than a corresponding width of the second substrate perpendicular to a length of the extension portion of the second dielectric layer and is configured to facilitate application of a mold compound to the first die and to the second die.

11. The power module of claim 10 , wherein the extension portion of the second dielectric layer and the extension portion of the first dielectric layer comprise substantially similar lengths.

12. The power module of claim 10 , wherein the extension portion of the second dielectric layer extends beyond the extension portion of the first dielectric and the lengths of the third and the fourth metal layers are longer than the lengths of the first and the second metal layers.

13. The semiconductor package of claim 10 , wherein the substrates are biased by two or more springs relative to a molding apparatus.

14. The semiconductor package of claim 10 , wherein each of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer comprise one of copper, aluminum and any combination thereof.

15. The semiconductor package of claim 10 , wherein the first die and the second die comprise one of a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a superjunction field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET) device, a silicon carbide (SiC) device, a SiC BJT, a diode, a Schottky diode, and combination thereof.

16. The power module of claim 10 , wherein the first electrical spacer is coupled with the second metal layer, the first die is coupled with the third me

Assignees

• Fairchild Semiconductor

Inventors

• Im Seungwon
• Jeon Oseob
• Son Joonseo
• Jong Mankyo
• Zschieschang Olaf

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title