Interconnect etch with polymer layer edge protection

Patent metadata

Field	Value
Publication number	US-10403589-B2
Application number	US-201715639812-A
Country	US
Kind code	B2
Filing date	Jun 30, 2017
Priority date	Apr 1, 2014
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.

First claim

What is claimed is:

1. A semiconductor workpiece, comprising:
first and second semiconductor chips separated by a dicing street;
a passivation structure over the first and second semiconductor chips;
a polymer layer on the passivation structure, the polymer layer having a first opening with opposing edges pulled back from the dicing street and a second opening that exposes a portion of the passivation structure over the first semiconductor chip whereby the polymer layer is operable to serve as an etch mask for an etch of the exposed portion; and
a mask over the first opening.

2. The semiconductor workpiece of claim 1 , wherein the mask fully covers the first opening.

3. The semiconductor workpiece of claim 1 , wherein the polymer layer comprises polyimide or benzocyclobutene.

4. The semiconductor workpiece of claim 1 , wherein the polymer layer contains a photoactive compound.

5. The semiconductor workpiece of claim 1 , wherein the mask comprises a third opening within the first opening, the third opening exposing a second portion of the passivation structure.

6. The semiconductor workpiece of claim 5 , wherein the third opening exposes a portion of the semiconductor workpiece.

7. The semiconductor workpiece of claim 1 , wherein the mask comprises a resist or a hard mask.

8. A silicon wafer, comprising:
first and second semiconductor chips separated by a dicing street;
a passivation structure over the first and second semiconductor chips;
a polyimide layer on the passivation structure, the polyimide layer having a first opening with opposing edges pulled back from the dicing street and a second opening in the polymer layer that exposes a portion of the passivation structure over the first semiconductor chip whereby the polyimide layer is operable to serve as an etch mask for an etch of the exposed portion; and
a mask over the first opening.

9. The silicon wafer of claim 8 , wherein the mask fully covers the first opening.

10. The silicon wafer of claim 8 wherein the polymer layer comprises polyimide or benzocyclobutene.

11. The silicon wafer of claim 8 , wherein the polymer layer contains a photoactive compound.

12. The silicon wafer of claim 8 , wherein the mask comprises a resist or a hard mask.

13. A silicon wafer, comprising:
first and second semiconductor chips separated by a dicing street;
a passivation structure over the first and second semiconductor chips;
a polyimide layer on the passivation structure, the polyimide layer having a first opening with opposing edges pulled back from the dicing street; and
a mask over the first opening, the mask including a third opening within the first opening, the third opening exposing a second portion of the passivation structure.

14. The silicon wafer of claim 13 , wherein the third opening exposes a portion of the silicon wafer.

Assignees

• Topacio Roden R
• Ati Technologies Ulc

Inventors

• Topacio Roden R

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title