High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He—N2 co-implantation

Patent metadata

Field	Value
Publication number	US-10403541-B2
Application number	US-201815977599-A
Country	US
Kind code	B2
Filing date	May 11, 2018
Priority date	Nov 18, 2014
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and comprises a region of nitrogen-reacted nanovoids in the front surface region; a silicon dioxide layer on the surface of the semiconductor handle substrate; a dielectric layer in contact with the silicon dioxide layer; and a semiconductor device layer in contact with the dielectric layer.

First claim

What is claimed is:

1. A method of forming a multilayer structure, the method comprising:
oxidizing a front surface of a single crystal semiconductor handle substrate to thereby prepare a semiconductor oxide layer having a thickness, D 1 , wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, a front surface region having a depth, D, as measured from the front surface and toward the central plane, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
implanting He through the semiconductor oxide and the front surface of the single crystal semiconductor handle substrate to form an implant plane having a peak depth, D 2 , as measured from the front surface of the single crystal semiconductor substrate toward the central plane;
implanting N 2 through the semiconductor oxide and the front surface of the single crystal semiconductor handle substrate to form an implant plane having a peak depth, D 3 , as measured from the front surface of the single crystal semiconductor substrate toward the central plane;
heating the He and N 2 implanted single crystal semiconductor handle substrate at a temperature and a duration sufficient to out-diffuse He and thereby yield nanovoids in the front surface region of the single crystal semiconductor handle substrate; and
bonding a dielectric layer on a front surface of a single crystal semiconductor donor substrate to the semiconductor oxide layer of the single crystal semiconductor handle substrate to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate, and further wherein the front surface of the semiconductor donor substrate comprises the dielectric layer.

2. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises silicon, and the semiconductor oxide comprises silicon dioxide.

3. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises a silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method, and the semiconductor oxide comprises silicon dioxide.

4. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 500 Ohm-cm and about 100,000 Ohm-cm.

5. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 1000 Ohm-cm and about 100,000 Ohm-cm.

6. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 1000 ohm-cm and about 10,000 Ohm-cm.

7. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 2000 Ohm-cm and about 10,000 Ohm-cm.

8. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 10,000 Ohm-cm.

9. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 5,000 Ohm-cm.

10. The method of claim 1 wherein the front surface region comprises nanovoids at a surface density of at least about 1×10 12 nitrogen-reacted nanovoids/cm 2 .

11. The method of claim 1 wherein the front surface region comprises nanovoids at a surface density between about 1×10 12 nitrogen-reacted nanovoids/cm 2 and about 1×10 15 nitrogen-reacted nanovoids/cm 2 .

12. The method of claim 1 wherein the front surface region comprises nanovoids at a surface density between about 1×10 13 nitrogen-reacted nanovoids/cm 2 and about 1×10 13 nitrogen-reacted nanovoids/cm 2 .

13. The method of claim 1 wherein the single crystal semiconductor donor substrate comprises a silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

14. The method of claim 1 wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof.

15. The method of claim 1 wherein the dielectric layer comprises a buried oxide layer having a thickness of at least about 10 nanometer thick.

16. The method of claim 1 wherein the dielectric layer comprises a buried oxide layer having a thickness between about 10 nanometers and about 10,000 nanometers.

17. The method of claim 1 wherein the dielectric layer comprises a buried oxide layer having a thickness between about 10 nanometers and about 5,000 nanometers.

18. The method of claim 1 wherein the dielectric layer comprises silicon dioxide.

19. The method of claim 18 wherein the silicon dioxide has a thickness of at least about 10 nanometer thick.

20. The method of claim 18 wherein the silicon dioxide has a thickness between about 10 nanometers and about 10,000 nanometers.

21. The method of claim 18 wherein the silicon dioxide has a thickness between about 10 nanometers and about 5,000 nanometers.

22. The method of claim 1 further comprising heating the bonded structure at a temperature and for a duration sufficient to strengthen the bond between the dielectric layer of the semiconductor donor structure and the semiconductor oxide on the front surface of the single semiconductor handle substrate.

23. The method of claim 1 wherein the single crystal semiconductor donor substrate comprises an ion implanted damage layer.

24. The method of claim 23 further comprising mechanically cleaving the bonded structure at the ion implanted damage layer of the single crystal semiconductor donor substrate to thereby prepare a cleaved structure comprising the single crystal semiconductor handle substrate, the semiconductor oxide layer, the dielectric layer in contact with the semiconductor oxide layer, and a single crystal semiconductor device layer with the dielectric layer.

25. The method of claim 24 further comprising heating the cleaved structure at a temperature and for a duration sufficient to strengthen the bond between the single crystal semiconductor device layer and the single crystal semiconductor handle substrate.

Assignees

• Sunedison Semiconductor Ltd Uen201334164H
• Globalwafers Co Ltd

Inventors

• Liu Qingmin
• Standley Robert Wendell

Classifications

• H10P95/405

  using cavities formed by hydrogen or noble gas ion implantation · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916 Primary

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H01L21/3223

  Electricity · mapped topic

• H01L21/76254 Primary

  Electricity · mapped topic