Processing method and device for multi-screen splicing display

Patent metadata

Field	Value
Publication number	US-10403237-B2
Application number	US-201715618754-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Dec 11, 2014
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A processing method and device for multi-screen splicing display are disclosed. The method includes: receiving instruction information for multi-screen splicing display, where the instruction information is used to instruct to splice at least two physical display screens for display; sending, according to the instruction information, display data to a video RAM of a virtual display screen formed by splicing the at least two physical display screens, where a size of the video RAM of the virtual display screen corresponds to a size of the virtual display screen; dividing the display data into at least two data blocks that correspond to sizes of the at least two physical display screens, and respectively sending the data blocks obtained by division to video RAMs of corresponding physical display screens.

First claim

What is claimed is:

1. A processing method for a multi-screen splicing display, comprising:
receiving instruction information for the multi-screen splicing display, wherein the instruction information is used to instruct to splice display data to be displayed on at least two physical display screens for display;
alternately sending, according to the instruction information, display data to at least two buffer units of a buffer of a video RAM of a virtual display screen formed by splicing the display data to be displayed on the at least two physical display screens, wherein a size of the video RAM of the virtual display screen corresponds to a size of the virtual display screen;
dividing the display data into at least two data blocks that correspond to sizes of the at least two physical display screens;
determining a frame synchronization signal having a highest frequency among frame synchronization signals of the at least two physical display screens as a frame synchronization signal of the virtual display screen;
respectively sending, according to the determined frame synchronization signal of the virtual display screen, the data blocks obtained by division to video RAMs of corresponding physical display screens from the display data sent to the at least two buffer units; and
outputting the data blocks received in the video RAMs of the at least two physical display screens to display hardware that corresponds to the at least two physical display screens for display.

2. The method according to claim 1 , before the alternatively sending, according to the instruction information, display data to the at least two buffer units of the buffer of the video RAM of the virtual display screen formed by splicing the display data to be displayed on the at least two physical display screens, further comprising:
obtaining parameter information of the virtual display screen, wherein the parameter information of the virtual display screen comprises the size of the virtual display screen and video RAM information of the virtual display screen.

3. The method according to claim 2 , after the obtaining parameter information of the virtual display screen, further comprising:
obtaining, according to the parameter information of the virtual display screen, that a size of a first virtual display screen is a first resolution, and a video RAM of the first virtual display screen is a first video RAM, wherein a size of the first video RAM corresponds to the first resolution, and the first resolution is less than a resolution of the virtual display screen; and
alternately sending, according to the instruction information, the display data to the at least two buffer units of the buffer of the video RAM of the virtual display screen comprises:
alternately sending, according to the instruction information, the display data to at least two buffer units of a buffer of the first video RAM; and
compiling the display data in the at least two buffer units of the buffer of the first video RAM to a central area of the virtual display screen.

4. The method according to claim 3 , after the compiling the image display data in the first video RAM to the central area of the virtual display screen, further comprising:
adding preset background display data to a video RAM that corresponds to an area outside the central area of the virtual display screen.

5. The method according to claim 1 , wherein
the at least two buffer units have a same size; and
alternately sending, according to the instruction information, display data to the at least two buffer units of the buffer comprises alternately sending display data that corresponds to each frame of the display data to the at least two buffer units according to a frame sequence of the display data.

6. A processing device for a multi-screen splicing display, comprising:
a non-transitory computer-readable storage medium configured to store instructions;
a processor configured to execute the instructions stored in the non-transitory computer-readable storage medium to receive instruction information for the multi-screen splicing display, wherein the instruction information is used to instruct to splice display data to be displayed on at least two physical display screens for display,
alternately send, according to the instruction information, display data to at least two buffer units of a buffer of a video RAM of a virtual display screen formed by splicing the display data to be displayed on the at least two physical display screens, wherein a size of the video RAM of the virtual display screen corresponds to a size of the virtual display screen, and
divide the display data into at least two data blocks that correspond to sizes of the at least two physical display screens,
determine a frame synchronization signal having a highest frequency among frame synchronization signals of the at least two physical display screens as a frame synchronization signal of the virtual display screen,
respectively send, according to the determined frame synchronization signal of the virtual display screen, the data blocks obtained by division to video RAMs of corresponding physical display screens from the display data sent to the at least two buffer units; and

a display module, configured to output the data blocks received in the video RAMs of the at least two physical display screens to display hardware that corresponds to the at least two physical display screens for display.

7. The device according to claim 6 , wherein
the processor is further configured to: before the display data is alternately sent, according to the instruction information, to the at least two buffer units of the buffer of the video RAM of the virtual display screen formed by splicing the display data to be displayed on the at least two physical display screens, obtain parameter information of the virtual display screen, and
the parameter information of the virtual display screen comprises the size of the virtual display screen and video RAM information of the virtual display screen.

8. The device according to claim 7 , wherein the processor is further configured to:
after obtaining the parameter information of the virtual display screen, obtain, according to the parameter information of the virtual display screen, that a size of a first virtual display screen is a first resolution, and a video RAM of the first virtual display screen is a first video RAM, wherein a size of the first video RAM corresponds to the first resolution, and the first resolution is less than that of the virtual display screen, and
alternately send, according to the instruction information, the display data to at least two buffer units of a buffer of the first video RAM, and compile the display data in the at least two buffer units of the buffer of the first video RAM to a central area of the virtual display screen.

9. The device according to claim 8 , wherein the processor is further configured to add preset background display data to a video RAM that corresponds to an area outside the central area of the virtual display screen.

10. The device according to claim 6 , wherein
the at least two buffer units have a same size, and
the processor is configured to alternately send, according to the instruction information, display data that corresponds to each frame of the display data to the at least two buffer units according to a frame sequence of the display data.

11. The device according to claim 6 , wherein the processor is configured to:
obtain a first resolution value of the virtual display screen according to a resolution value of each of the at least two physical display screens,
determine whether the first resolution value is a supporte

Assignees

• Huawei Tech Co Ltd

Inventors

• Chen Lei

Classifications

• G06F3/1423

  controlling a plurality of local displays, e.g. CRT and flat panel display · CPC title

• G09G5/12

  Synchronisation between the display unit and other units, e.g. other display units, video-disc players · CPC title

• G09G5/14 Primary

  Display of multiple viewports · CPC title

• G09G2340/0407

  Resolution change, inclusive of the use of different resolutions for different screen areas · CPC title

• G09G5/399

  using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers · CPC title