Array substrate, electrical aging method, display device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10403209-B2
Application number	US-201615244830-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Jan 28, 2016
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

An array substrate, an electrical aging method, a display device and a manufacturing method thereof. The array substrate includes: pixel circuits disposed in a display area, where each of the pixel circuits is disposed in a corresponding pixel region of the display area; a scanning drive circuit disposed outside the display area; a plurality of scanning-line groups for connecting the pixel circuits to the scanning drive circuit; a voltage input interface disposed outside the display area; and a wire group for connecting the plurality of scanning-line groups to the voltage input interface. An insulating layer is disposed between the wire group and the scanning drive circuit.

First claim

What is claimed is:

1. An array substrate, comprising:
pixel circuits in a display area;
a scanning drive circuit on at least one side of the pixel circuits in a periphery area surrounding the display area;
a plurality of scanning-line groups for connecting the pixel circuits to the scanning drive circuit;
a wire group, comprising a first wire sub-group and a second wire sub-group, wherein the first wire sub-group is opposite to the scanning drive circuit, the first wire sub-group comprises a first terminal and a second terminal; and
an insulating layer disposed between the first wire sub-group and the scanning drive circuit;
wherein the first terminal is directly connected to the scanning drive circuit and the pixel circuits, and
the second terminal is disconnected from the second wire sub-group which has been cut off and is originally coupled to the first wire sub-group.

2. The array substrate according to claim 1 , wherein each of the pixel circuits includes an organic light-emitting diode (OLED) disposed between a first bias electrode and a second bias electrode to form a drive current path.

3. A display device, comprising the array substrate according to claim 1 .

4. A method for manufacturing a display device, with the display device including the array substrate according to claim 1 , the array substrate including a cut-off area disposed at an edge of the array substrate, and a wiring path of each wire in the second wire sub-group running through the cut-off area, the method comprising:
removing the cut-off area to cut off each wire in the second wire sub-group after electrical aging of the pixel circuits on the array substrate.

5. The method for manufacturing the display device according to claim 4 , further comprising:
cutting off each wire in the second wire sub-group with laser.

6. An array substrate, comprising:
pixel circuits disposed in a display area;
a scanning drive circuit disposed on at least one side of pixel circuits in a periphery area surrounding the display area;
a plurality of scanning-line groups for connecting the pixel circuits to the scanning drive circuit;
a voltage input interface disposed outside the display area; and
a wire group, comprising a first wire sub-group and a second wire sub-group, wherein the first wire sub-group is opposite to the scanning drive circuit, the second wire sub-group is in a cut-off area, the cut-off area is at a side of the periphery area far away from the display area;
wherein an insulating layer is disposed between the first wire sub-group and the scanning drive circuit,
wherein the first wire sub-group is directly connected to the scanning drive circuit and the pixel circuits, and
wherein the second wire sub-group is connected to the first wire sub-group and a voltage input interface in the periphery area.

7. The array substrate according to claim 6 , wherein the array substrate comprises the cut-off area disposed at an edge of the array substrate, and a wiring path of each wire in the second wire sub-group runs through the cut-off area.

8. The array substrate according to claim 7 , wherein circuit nodes of each wire in the second wire sub-group that connect corresponding scanning lines to the wire are disposed in the cut-off area.

9. The array substrate according to claim 6 , wherein each of the pixel circuits includes an organic light-emitting diode (OLED) disposed between a first bias electrode and a second bias electrode to form a drive current path.

10. The array substrate according to claim 9 , wherein:
each of the pixel circuits further includes a driving transistor and a first transistor, and each scanning-line group includes a first scanning line;
a source electrode and a drain electrode of the driving transistor are disposed in the drive current path;
one of a source electrode and a drain electrode of the first transistor is connected with a gate electrode of the driving transistor, and the other of the source electrode and the drain electrode of the first transistor is connected with a data line; and
a gate electrode of the first transistor is connected with the scanning drive circuit through the first scanning line, a first wire in the first wire sub-group is connected with the first scanning line, and a first voltage input port of the voltage input interface is connected with the first wire.

11. The array substrate according to claim 10 , wherein:
each of the pixel circuits further includes a second transistor, each scanning-line group further includes a second scanning line;
one of a source electrode and a drain electrode of the second transistor is connected with the gate electrode of the driving transistor, and the other of the source electrode and the drain electrode of the second transistor is connected with an initial voltage line;
a gate electrode of the second transistor is connected with the scanning drive circuit through the second scanning line;
a second wire in the first wire sub-group is connected with the second scanning line; and
a second voltage input port of the voltage input interface is connected with the second wire.

12. The array substrate according to claim 9 , wherein:
each of the pixel circuits further includes a third transistor with a source electrode and a drain electrode being disposed in the drive current path, and each scanning-line group includes a third scanning line;
a gate electrode of the third transistor is connected with the scanning drive circuit through the third scanning line;
a third wire in the first wire sub-group is connected with the third scanning line; and
a third voltage input port of the voltage input interface is connected with the third wire.

13. A display device, comprising the array substrate according to claim 6 .

14. An electrical aging method of pixel circuits, with the pixel circuits being disposed in pixel regions of a display area of the array substrate according to claim 6 , comprising:
applying aging voltage signals to voltage input ports of the voltage input interface respectively, so that at least part of transistors in the pixel circuits are subjected to electrical aging in response to application of the aging voltage signals received by gate electrodes of the transistors;
wherein the aging voltage signals are the plurality of scanning drive signals.

15. A method for manufacturing a display device, with the display device including the array substrate according to claim 6 , the array substrate including the cut-off area disposed at the edge of the array substrate, and a wiring path of each wire in the second wire sub-group running through the cut-off area, the method comprising:
removing the cut-off area to cut off each wire in the second wire sub-group after electrical aging of the pixel circuits on the array substrate.

16. The method for manufacturing the display device according to claim 15 , further comprising:
cutting off each wire in the second wire sub-group with laser.

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Wang Jun
• Jin Xinxin
• Qu Yi
• Zhang Yi
• Cheng Tianyi

Classifications

• G09G2330/04

  Display protection · CPC title

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

• G09G2310/0254

  Control of polarity reversal in general, other than for liquid crystal displays · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title