Optimizing for rendering with clear color

Patent metadata

Field	Value
Publication number	US-10403024-B2
Application number	US-201815988157-A
Country	US
Kind code	B2
Filing date	May 24, 2018
Priority date	Jun 11, 2015
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

First claim

What is claimed is:

1. A graphics processing system comprising:
a register storing a clear color value;
a frame buffer comprising a plurality of cache lines, each cache line storing a plurality of color values for pixels in a block of the frame buffer;
a set of control bits, each control bit representing one or more states of one or more cache lines; and
a processor coupled to the register, frame buffer and set of control bits and configured to
clear one or more cache lines of the frame buffer by setting each control bit representing states of the one or more cache lines to a clear state, and
read the clear color value from the register for any read requests to the one or more cache lines represented by a control bit in the clear state.

2. The graphics processing system of claim 1 , wherein each control bit represents states further including a data state of the one or more cache lines.

3. The graphics processing system of claim 2 , wherein the processor is further configured to render one or more blocks of the frame buffer with a color other than the clear color and to set each control bit representing the one or more cache lines of the one or more blocks of the frame buffer to the data state.

4. The graphics processing system of claim 1 , wherein the processor is configured to detect a write request of the clear color to one or more cache lines of the frame buffer and to set each control bit representing a state of the one or more cache lines to the clear state if the write request of the clear color is detected.

5. The graphics processing system of claim 4 , wherein the write request of the clear color value to the one or more cache lines of the frame buffer is skipped.

6. The graphics system of claim 4 , wherein each control bit represents states further including a compressed state of the one or more cache lines.

7. The graphics system of claim 6 , wherein the processor is configured to detect the write request of the clear color value to one or more cache lines in the compressed state.

8. A non-transitory machine-readable medium storing instructions which, when executed by one or more processors, causes the one or more processors to perform an operation comprising:
storing a clear color value in a register;
clearing one or more cache lines of a frame buffer by setting each control bit in a set of control bits representing one or more states of the one or more cache lines in a clear state, wherein each cache line stores a plurality of color values for pixels in a block of the frame buffer; and
reading the clear color value from the register for any read requests to the one or more cache lines represented by a control bit in the clear state.

9. The non-transitory machine-readable medium of claim 8 , wherein the one or more processors perform an operation comprising:
rendering one or more blocks of the frame buffer with a color other than the clear color value; and
setting each control bit representing the one or more cache lines of the one or more blocks of the frame buffer to the data state.

10. The non-transitory machine-readable medium of claim 9 , wherein the one or more processors perform an operation comprising:
detecting a write request of the clear color to one or more cache lines of the frame buffer; and
setting each control bit representing a state of the one or more cache lines to the clear state if the write request of the clear color is detected.

11. The non-transitory machine-readable medium of claim 10 , wherein the one or more processors perform an operation comprising:
skipping the write request of the clear color to the one or more cache lines of the frame buffer.

12. The non-transitory machine-readable medium of claim 11 , wherein the one or more processors perform an operation comprising:
setting one or more control bits to a compressed state for one or more cache lines.

13. The non-transitory machine-readable medium of claim 12 , wherein the one or more processors perform an operation comprising:
detecting the write request of the clear color value to one or more cache lines in the compressed state.

14. A graphics processor comprising:
a register storing a clear color value;
a frame buffer comprising a plurality of blocks of memory, each block of memory storing a plurality of color values for pixels in the block;
a set of control bits, each control bit representing one or more states of one or more blocks of memory; and
render logic coupled to the register, frame buffer and set of control bits and configured to
clear blocks of memory of the frame buffer by setting each control bit representing states of the one or more blocks of memory to a clear state, and
read the clear color value from the register for any read requests to the one or more blocks of memory represented by a control bit in the clear state.

15. The graphics processor of claim 14 , wherein each control bit represents states further including a data state of the one or more blocks of memory.

16. The graphics processor of claim 15 , wherein the render logic is further configured to render one or more blocks of memory of the frame buffer with a color other than the clear color value and to set each control bit representing the one or more blocks of memory to the data state.

17. The graphics processor claim 14 , wherein the render logic is further configured to detect a write request of the clear color value to one or more blocks of memory and to set each control bit representing a state of the one or more blocks to the clear state if the write request of the clear color is detected.

18. The graphics processor of claim 17 , wherein the render logic is further configured to skip the write request of the clear color value to the one or more blocks of memory.

19. The graphics processor of claim 17 , further comprising:
compression logic to compress color values of the one or more blocks of memory.

20. The graphics processor of claim 19 , wherein the render logic is further configured to detect the write request of the clear color to one or blocks of memory based on the compressed color values.

Assignees

• Intel Corp

Inventors

• Poddar Bimal
• Surti Prasoonkumar
• Sathe Rahul P

Classifications

• G06T19/20

  Editing of three-dimensional [3D] images, e.g. changing shapes or colours, aligning objects or positioning parts · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06T15/506

  Illumination models · CPC title

• G06T2200/04

  involving 3D image data · CPC title