Nonvolatile memory apparatus and verification write method thereof for reducing program time

Patent metadata

Field	Value
Publication number	US-10402098-B2
Application number	US-201615275623-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Mar 14, 2016
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A non-volatile memory apparatus may include a program current generation circuit, a clamping circuit and a voltage generation circuit. The program current generation circuit may increase a program current based on a memory cell current flowing through a memory cell. The clamping circuit may clamp the memory cell current. The voltage generation circuit may apply a voltage corresponding to a verification-write voltage to the memory cell. Therefore, the verification-write operation may be performed to the memory cell.

First claim

What is claimed is:

1. A non-volatile memory apparatus comprising:
a voltage generation circuit coupled to a memory cell and configured to provide a voltage corresponding to a verification-write voltage to the memory cell when a reset program operation is performed, wherein the verification-write voltage is a voltage at which a snap-back of the memory cell in a reset state does not occur, and has a higher voltage level than a read voltage;
a program current generation circuit configured to increase a program current when the snap-back occurs, and to end a program operation without the program current flowing through the memory cell when the snap-back does not occur; and
a clamping circuit coupled to the voltage generation circuit and configured to clamp the memory cell current to maintain a range of a memory cell current below the program current for the reset program operation.

2. The non-volatile memory apparatus of claim 1 , further comprising a sense amplifier configured to generate a detection signal by detecting whether the snap-back occurs, wherein the program current generation circuit includes:
a program controller configured to generate a current update signal and a program end signal based on the detection signal; and
a clamping controller configured to generate a clamping control signal by increasing the program current according to the current update signal.

3. The non-volatile memory apparatus of claim 2 , wherein the sense amplifier generates the detection signal having a first level when the memory cell current is greater than a threshold current value, and generates the detection signal having a second level when the memory cell current is less than the threshold current value.

4. The non-volatile memory apparatus of claim 2 , wherein the program controller increases a value of the current update signal every time the program controller receives the detection signal having a first level.

5. The non-volatile memory apparatus of claim 4 , wherein the program controller counts a number of the detection signal having the first level, and generates the program end signal when the number of the detection signal reaches a maximum.

6. The non-volatile memory apparatus of claim 4 , wherein the program controller generates the program end signal when the value of the current update signal reaches a maximum.

7. The non-volatile memory apparatus of claim 4 , wherein the program controller generates the program end signal in response to the detection signal having a second level.

8. The non-volatile memory apparatus of claim 2 , wherein the clamping controller includes:
a variable current source configured to increase the program current based on the current update signal; and
a clamping control signal generator configured to generate the clamping control signal having a voltage level corresponding to an amount of the program current.

9. The non-volatile memory apparatus of claim 2 , wherein the clamping circuit applies a clamping current substantially same as the program current to the voltage generation circuit in response to the clamping control signal.

10. A non-volatile memory apparatus comprising:
a clamping circuit configured to prevent a memory cell current flowing through a memory cell from exceeding a program current for a reset program operation in response to a clamping control signal;
a voltage generation circuit configured to receive a verification-write voltage and apply a sensing voltage to the memory cell when the reset program operation is performed, wherein the verification-write voltage is a voltage at which a snap-back of the memory cell in a reset state does not occur, and has a higher voltage level than a read voltage;
a sense amplifier configured to generate a detection signal by detecting whether the snap-back of the memory cell occurs;
a program controller configured to generate a current update signal and a program end signal based on the detection signal; and
a clamping controller configured to generate the clamping control signal by increasing the program current according to the current update signal.

11. The non-volatile memory apparatus of claim 10 , wherein the program controller increases a value of the current update signal every time the program controller receives the detection signal having a first level.

12. The non-volatile memory apparatus of claim 10 , wherein the program controller counts a number of the detection signal having a first level, and generates the program end signal when the number of the detection signal reaches a maximum.

13. The non-volatile memory apparatus of claim 10 , wherein the program controller generates the program end signal when the value of the current update signal reaches a maximum.

14. The non-volatile memory apparatus of claim 10 , wherein the program controller generates the program end signal in response to the detection signal having a second level.

15. The non-volatile memory apparatus of claim 10 , wherein the clamping controller includes:
a variable current source configured to increase the program current based on the current update signal; and
a clamping control signal generator configured to generate the clamping control signal having a voltage level corresponding to an amount of the program current.

16. The non-volatile memory apparatus of claim 10 , wherein the clamping circuit applies a clamping current substantially same as the program current to the voltage generation circuit in response to the clamping control signal.

Assignees

• Sk Hynix Inc

Inventors

• Cheon Jun Ho

Classifications

• G11C2213/15

  Current-voltage curve · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C2013/0078

  Write using current through the cell · CPC title

• G11C2013/0066

  Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing · CPC title