Reference voltage sub-system allowing fast power up from extended periods of ultra-low power standby mode

Patent metadata

Field	Value
Publication number	US-10401942-B2
Application number	US-201715439887-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Feb 22, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.

First claim

What is claimed is:

1. A reference voltage facility comprising:
said reference voltage facility operable in a first mode which is active mode, said reference voltage facility operable in a second mode which is standby mode;
a reference voltage buffer adapted to develop a first reference voltage;
a reference voltage keeper adapted to develop a second reference voltage as a function of a trim control signal, said trim control signal comprising a set of n-bit trim codes;
an active calibration facility adapted to:
in said first mode, by a comparator, comparing said first reference voltage with said second reference voltage, and:
when said first reference voltage exceeds said second reference voltage, said
comparator providing comparator output comprising a first logic value,
when said first reference voltage is less than said second reference voltage, said
comparator providing comparator output comprising a second logic value;

in said first mode, by a state machine, receive said comparator output;
in said first mode, by said state machine, develop said set of n-bit trim codes as a function of said comparator output;
in said first mode, by said comparator, repeat said comparing until said second reference voltage is less than said first reference voltage;
in said first mode, by said state machine, adjust said set of n-bit trim codes upon said repeat, as follows:
if said second reference voltage is less than said first reference voltage, adjust said set of n-bit trim codes to cause a keeper receiving said set of n-bit trim codes to increase said second reference voltage;
if said second reference voltage is greater than said first reference voltage, adjust said set of n-bit trim codes to cause a keeper receiving said set of n-bit trim codes to decrease said second reference voltage;
in said first mode, if said second reference voltage is less than said first reference voltage, store said set of n-bit trim codes for use in said second mode;
in said second mode, said state machine holding constant said set of n-bit trim codes at values last stored in said first mode;

a first selector switch adapted to provide a selected one of said first and second reference voltages; and
a reservoir capacitor adapted to:
receive said selected one of said first and second reference voltages; and
operate to:
store said selected one of said first and second reference voltages; and
smooth fluctuations in said selected one of said first and second reference voltages.

2. The reference voltage facility of claim 1 comprising:
said keeper comprising a feedback network, said feedback network comprising a tunable divider network, said tunable divider network trimmed as a function of said set of n-bit trim codes.

3. The reference voltage facility of claim 2 comprising:
said tunable divider network comprising an adjustable resistive element, said adjustable resistive element trimmed as a function of said set of n-bit trim codes.

4. The reference voltage facility of claim 1 wherein said first reference voltage and said second reference voltage are different by between 5 mV and 30 mV.

5. A method of operating a reference voltage facility, said reference voltage facility operable in a first mode which is active mode, said reference voltage facility operable in a second mode which is standby mode, said method comprising the steps of:
developing, by a reference voltage buffer, a first reference voltage;
developing, by a reference voltage keeper, a second reference voltage as a function of a trim control signal, said trim control signal comprising a set of n-bit trim codes;
in an active calibration facility:
in said first mode:
comparing, by a comparator, said first reference voltage to the second reference voltage;
providing, by said comparator, when said first reference voltage exceeds said second reference voltage, comparator output comprising a first logic value,
providing, by said comparator, when said first reference voltage is less than said second reference voltage, comparator output comprising a second logic value;
receiving, by a state machine, said comparator output;
developing, by said state machine, said set of n-bit trim codes as a function of said comparator output;
repeating, by said comparator, said comparing until said second reference voltage is less than said first reference voltage;
adjusting, by said state machine, said set of n-bit trim codes upon said repeating, as follows:
if said second reference voltage is less than said first reference voltage, adjusting said set of n-bit trim codes to cause a keeper receiving said set of n-bit trim codes to increase the second reference voltage; and
if said second reference voltage is greater than said first reference voltage, adjusting said set of n-bit trim codes to cause a keeper receiving said set of n-bit trim codes to decrease the second reference voltage;

storing, if said second reference voltage is less than said first reference voltage, said set of n-bit trim codes for use in said second mode;

in said second mode:
holding constant, by said state machine, said set of n-bit trim codes at values last stored in said first mode;

providing a selected one of the first and second reference voltages;
storing said selected one of the first and second reference voltages; and
smoothing said selected one of the first and second reference voltages.

6. The method of claim 5 comprising:
said adjusting comprising:
said keeper comprising a feedback network, said feedback network comprising a tunable divider network, said tunable divider network trimmed as a function of said set of n-bit trim codes.

7. The method of claim 6 comprising:
said tunable divider network comprising an adjustable resistive element, said adjustable resistive element trimmed as a function of said set of n-bit trim codes.

8. The method of claim 5 wherein said first reference voltage and said second reference voltage are different by between 5 mV and 30 mV.

9. A reference voltage facility configured to perform the steps of a method according to any one of claims 5 to 8 .

10. A computing system comprising a voltage reference facility according to claim 9 .

11. A non-transitory computer readable medium including executable instructions which, when executed in a processing system, causes the processing system to perform the steps of a method according to any one of claims 5 to 8 .

Assignees

• Ambiq Micro Inc

Inventors

• Bogue Ivan
• Lu Yanning
• Mandyam Bharath

Classifications

• H03M1/204

  in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators · CPC title

• H03M1/203

  using an analogue interpolation circuit · CPC title

• H03M1/185

  the determination of the range being based on more than one digital output value, e.g. on a running average, a power estimation or the rate of change · CPC title

• H03M1/007

  among different resolutions · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title