Thermal sensor placement for hotspot interpolation

Patent metadata

Field	Value
Publication number	US-10401235-B2
Application number	US-201514852350-A
Country	US
Kind code	B2
Filing date	Sep 11, 2015
Priority date	Sep 11, 2015
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

In one embodiment, a temperature management system comprises a plurality of thermal sensors at different locations on a chip, and a temperature manager. The temperature manager is configured to receive a plurality of temperature readings from the thermal sensors, to fit a quadratic temperature model to the received temperature readings, and to estimate a hotspot temperature on the chip using the fitted quadratic temperature model.

First claim

What is claimed is:

1. A temperature management system, comprising:
a plurality of thermal sensors at different locations on a chip, the chip including a processor, wherein thermal sensors of the plurality of thermal sensors are configured to provide a plurality of temperature readings, wherein the thermal sensors of the plurality of thermal sensors are all located outside of the processor, wherein at least three of the thermal sensors of the plurality of thermal sensors are aligned along a line to enable interpolation of temperatures at locations on or near the line, and wherein the line is positioned to intersect a portion of the processor to enable estimation of a hotspot temperature on the chip at a location within the processor; and
a temperature manager configured to receive the plurality of temperature readings from the thermal sensors of the plurality of thermal sensors, to fit a temperature model to the received temperature readings, and to estimate the hotspot temperature on the chip using the fitted temperature model, wherein the estimated hotspot temperature corresponds to the location within the processor.

2. The system of claim 1 , wherein the temperature manager is configured to
estimate the hotspot temperature by determining a peak temperature using the fitted temperature model.

3. The system of claim 2 , wherein the fitted temperature model is a fitted quadratic temperature model, and wherein the temperature manager is configured to determine the peak temperature by setting a derivative of the fitted quadratic temperature model to zero to determine a location corresponding to the peak temperature, and inputting the determined location to the fitted quadratic temperature model to determine the peak temperature.

4. The system of claim 2 , wherein the temperature manager is configured to determine the peak temperature by determining a plurality of temperatures at a plurality of different locations on the chip using the fitted temperature model, and selecting a highest one of the determined temperatures.

5. The system of claim 1 , wherein the temperature manager is configured compare the estimated hotspot temperature to a temperature threshold, and to initiate temperature mitigation if the estimated hotspot temperature exceeds the temperature threshold.

6. The system of claim 5 , wherein the temperature manager is configured to initiate temperature mitigation by commanding a clock source to reduce a frequency of a clock signal, commanding a power source to reduce a supply voltage, or both.

7. A method for managing temperature, comprising:
receiving a plurality of temperature readings from thermal sensors of a plurality of thermal sensors, wherein the thermal sensors of the plurality of thermal sensors are at different locations on a chip, wherein the thermal sensors of the plurality of thermal sensors are all located outside of a processor on the chip, wherein at least three of the thermal sensors of the plurality of thermal sensors are aligned along a line to enable interpolation of temperatures at locations on or near the line, and wherein the line is positioned to intersect a portion of the processor to enable estimation of a hotspot temperature on the chip at a location within the processor;
fitting a temperature model to the received temperature readings; and
estimating the hotspot temperature on the chip using the fitted temperature model, wherein the estimated hotspot temperature corresponds to the location within the processor.

8. The method of claim 7 ,
wherein estimating the hotspot temperature comprises determining a peak temperature using the fitted temperature model.

9. The method of claim 8 , wherein the fitted temperature model is a fitted quadratic temperature model, and wherein determining the peak temperature comprises setting a derivative of the fitted quadratic temperature model to zero to determine a location corresponding to the peak temperature, and inputting the determined location to the fitted quadratic temperature model to determine the peak temperature.

10. The method of claim 8 , wherein determining the peak temperature comprises determining a plurality of temperatures at a plurality of different locations on the chip using the fitted temperature model, and selecting a highest one of the determined temperatures.

11. The method of claim 7 , further comprising comparing the estimated hotspot temperature to a temperature threshold, and initiating temperature mitigation if the estimated hotspot temperature exceeds the temperature threshold.

12. The method of claim 11 , wherein initiating temperature mitigation comprises commanding a clock source to reduce a frequency of a clock signal, commanding a power source to reduce a supply voltage, or both.

13. An apparatus for managing temperature, comprising:
means for receiving a plurality of temperature readings from thermal sensors of a plurality of thermal sensors, wherein the thermal sensors of the plurality of thermal sensors are at different locations on a chip, wherein the thermal sensors of the plurality of thermal sensors are all located outside of a processor on the chip, wherein at least three of the thermal sensors of the plurality of thermal sensors are aligned along a line to enable interpolation of temperatures at locations on or near the line, and wherein the line is positioned to intersect a portion of the processor to enable estimation of a hotspot temperature on the chip at a location within the processor;
means for fitting a temperature model to the received temperature readings; and
means for estimating the hotspot temperature on the chip using the fitted temperature model, wherein the estimated hotspot temperature corresponds to the location within the processor.

14. The apparatus of claim 13 ,
wherein the means for estimating the hotspot temperature comprises means for determining a peak temperature using the fitted temperature model.

15. The apparatus of claim 14 , wherein the fitted temperature model is a fitted quadratic temperature model, and wherein the means for determining the peak temperature comprises means for setting a derivative of the fitted quadratic temperature model to zero to determine a location corresponding to the peak temperature, and means for inputting the determined location to the fitted quadratic temperature model to determine the peak temperature.

16. The apparatus of claim 14 , wherein the means for determining the peak temperature comprises means for determining a plurality of temperatures at a plurality of different locations on the chip using the fitted temperature model, and means for selecting a highest one of the determined temperatures.

17. The apparatus of claim 13 , further comprising means for comparing the estimated hotspot temperature to a temperature threshold, and means for initiating temperature mitigation if the estimated hotspot temperature exceeds the temperature threshold.

18. The apparatus of claim 17 , wherein the means for initiating temperature mitigation comprises means for commanding a clock source to reduce a frequency of a clock signal, means for commanding a power source to reduce a supply voltage, or both.

19. A computer-readable medium comprising instructions stored thereon that, when executed by a processor, cause the processor to:
receive a plurality of temperature readings from thermal sensors of a plurality of thermal sensors, wherein the thermal sensors of the plurality of thermal sensors are at different locations on a chip, wherein the thermal sensors of the plurality of

Assignees

• Qualcomm Inc

Inventors

• Coutts Ryan Michael
• Mittal Rajat
• Saeidi Mehdi
• Penzes Paul Ivan

Classifications

• G06F2201/81

  Threshold · CPC title

• G06F11/3093

  Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes · CPC title

• G06F11/3058 Primary

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324

  by lowering clock frequency · CPC title