Fractional-N phase lock loop apparatus and method using multi-element fractional dividers

Patent metadata

Field	Value
Publication number	US-10396808-B2
Application number	US-201716084997-A
Country	US
Kind code	B2
Filing date	Mar 15, 2017
Priority date	Mar 15, 2016
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

The exemplified technology provides a circuit and clock synthesis technique that suppresses quantization noise in a ΔΣ fractional-N phase-locked loop (PLL) using a fineresolution multi-element fractional divider. The circuit and clock synthesis method beneficially suppresses noise uniformly over the entire frequency range. The circuit can be implemented using mostly digital circuitry, and is applicable for use with both analog and digital PLLs. With an 8-element fractional divider, it is observed that the circuit and clock synthesis technique can suppress quantization noise while incurring only a small increase in hardware complexity.

First claim

What is claimed is:

1. A frequency synthesizing circuit configured to synthesize an output signal, having an output frequency, from an input reference signal having an input reference frequency, wherein the output frequency has a multiplication factor to the input reference frequency, the frequency synthesizing circuit comprising:
a first set of one or more divider circuits, each configured to fractionally divide, in a feedback loop of a phase lock loop circuit, the output signal to generate a first fractional frequency signal, the first fractional frequency signal having a first frequency;
a second set of one or more divider circuits, each configured to fractionally divide, in the feedback loop of the phase lock loop circuit, the output signal to generate a second fractional frequency signal, the second fractional frequency signal having a second frequency, wherein the first frequency is not the same as the second frequency, and wherein the fractional frequency signals of the first and second sets of divider circuits are selectively combined to generate the output signal; and
a selector circuit coupled to each of the plurality of divider circuit, the selector circuit configured to generate one or more modulated selection signals to the first and second sets of divider circuits for selection of the output thereof, wherein the modulated selection signals are scrambled by a dynamic element matching circuit to produce an average distribution of the selection of each of the divider circuits of the first and second sets of divider circuits that are the same.

2. The frequency synthesizing circuit of claim 1 , wherein the fractional frequency signal generated by each of the first set of one or more divider circuits has a division ratio of N+1 to the output frequency, and wherein the fractional frequency signal generated by each of the second set of one or more divider circuits has a division factor of N to the output frequency.

3. The frequency synthesizing circuit of claim 2 , wherein the output frequency of the output signal has a multiplication factor of N+α value to the input reference frequency of the input reference signal, wherein N is an integer and α is a fraction value.

4. The frequency synthesizing circuit of claim 2 ,
wherein the first set of one or more divider circuits includes a k number of divider circuits, each configured to output the fractional frequency signal having the division ratio of N+1 to the output frequency, and
wherein the second set of one or more divider circuits includes a k−M number, each configured to output the fractional frequency signal having the division ratio of N to the output frequency, wherein M is a total number of divider circuits.

5. The frequency synthesizing circuit of claim 1 , comprising:
a third set of one or more divider circuits, each configured to output the fractional frequency signal having the division ratio of N+2 to the output frequency; and
a fourth set of one or more divider circuits, each configured to output the fractional frequency signal having the divisional ratio of N−1 to the output frequency,
wherein the fractional frequency signals of the first, second, third, and fourth sets of divider circuits are selectively combined to generate the output signal.

6. The frequency synthesizing circuit of claim 5 , wherein each of third set of one or more divider circuits is configured to output the fractional frequency signal having the division ratio of N−1 to the output frequency, and
wherein each of the fourth set of one or more divider circuits is configured to output the fractional frequency signal having the division ratio of N+2 to the output frequency.

7. The frequency synthesizing circuit of claim 1 , wherein the first and second sets of one or more divider circuits, collectively, has an average division ratio of N(1+α), wherein α is a fractional part of the division ratio.

8. The frequency synthesizing circuit of claim 1 , wherein the selector circuit comprises the dynamic element matching (DEM) circuit comprising:
i) a barrel shifter circuit configured to high-pass shape mismatch errors, among an input modulator signal, to the first order; or
ii) a vector quantizer circuit configured to shape mismatch error, among an input modulator signal, to higher orders.

9. The frequency synthesizing circuit of claim 1 , wherein the selector circuit comprises:
the dynamic element matching (DEM) circuit; and
a fractional delta-sigma modulator circuit coupled thereto,
wherein the fractional delta-sigma modulator is configured to generate the modulated selection signal.

10. The frequency synthesizing circuit of claim 1 , wherein the output signal comprises a fractional-N PLL (phase-lock loop) signal or a fractional-N CLK (clock) signal.

11. The frequency synthesizing circuit of claim 1 , wherein a combined number of dividers of the first and second sets of the divider circuits is a number selected from the group consisting of 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, and 32.

12. The frequency synthesizing circuit of claim 1 , wherein a combined number of dividers of the first and second sets of the divider circuits is an integer number greater than 24.

13. The frequency synthesizing circuit of claim 1 , comprising:
in the feedback loop:
a plurality of phase frequency detectors, each having an input that is coupled to an output of a respective divider circuit of the first and second sets of one or more divider circuits;
a plurality of charge pump element, each having an input that is coupled to an output of a respective phase frequency detector of the plurality of phase frequency detectors;
a loop filter having an input coupled to an output of the plurality of charge pump element; and
a voltage controlled oscillator having an input coupled to an output of the loop filter, wherein an output of the voltage controlled oscillator is coupled to an input of the first and second sets of one or more divider circuits.

14. The frequency synthesizing circuit of claim 1 , comprising:
in the feedback loop:
a plurality of time-to-digital converters (TDCs), each having an input that is coupled to an output of a respective divider circuit of the first and second sets of one or more divider circuits;
a plurality of digital summer elements, each having an input that is coupled to an output of a respective time-to-digital converters of the plurality of time-to-digital converters;
a loop filter having an input coupled to an output of the plurality of digital summer elements; and
a digitally controlled oscillator (DCO) having an input coupled to an output of the loop filter, wherein an output of the digitally controlled oscillator is coupled to an input of the first and second sets of one or more divider circuits.

15. The frequency synthesizing circuit of claim 14 , wherein the time-to-digital converter (TDC) is configured to support a wide swing covering at least one VCO period, and wherein the time-to-digital converter has a resolution and linearity in which quantization noise is prevented from folding into a PLL band.

16. The frequency synthesizing circuit of claim 14 , wherein instantaneous transition rate of any capacitor of the digitally controlled oscillator is ensured to be independent of digital control signal associated with the frequency synthesizing circuit.

17. The frequency synthesizing circuit of claim 14 , wherein the digitally controlled oscillator includes a feedback loop that guarantees that the all capacitor elements are used uniformly to simu

Assignees

• Univ Texas

Inventors

• Sun Nan

Classifications

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/1974 Primary

  for fractional frequency division · CPC title